A digitally controlled 2.4-GHz oscillator in 65-nm CMOS

  • Liangge Xu
  • Saska Lindfors
  • Kari Stadius
  • Jussi Ryynänen
Article

DOI: 10.1007/s10470-008-9178-5

Cite this article as:
Xu, L., Lindfors, S., Stadius, K. et al. Analog Integr Circ Sig Process (2009) 58: 35. doi:10.1007/s10470-008-9178-5

Abstract

This article presents a 2.4-GHz digitally controlled oscillator (DCO) for the ISM band. The circuit is designed using a 65-nm CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. The measured total frequency range is from 2.26 to 3.04 GHz. Its frequency quantization step is approximately 20 kHz, and using a digital ΣΔ-modulator (SDM), its effective frequency resolution is better than 1 kHz. Current consumption of the oscillator core is tunable through a 6-bit digital word. The measured phase noise is −122 dBc/Hz at 1-MHz offset frequency with 4.8-mA current consumption.

Keywords

DCO LC oscillator Digital control Sigma–delta modulator SDM LSB dithering Capacitance dithering Varactor bank CMOS 

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Liangge Xu
    • 1
  • Saska Lindfors
    • 1
  • Kari Stadius
    • 1
  • Jussi Ryynänen
    • 1
  1. 1.Department of Micro- and NanotechnologyHelsinki University of Technology/SMARAD2HelsinkiFinland

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