Automatic DC operating point computation and design plan generation for analog IPs
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DC operating point computation is inescapable for both knowledge-based and simulation-based analog synthesis. In this perspective, this article presents the automatic computation of DC operating point and the␣generation of suitable design plans for analog IPs. The analog IP is built as a hierarchy of subcircuits inside our dedicated framework CAIRO+. Leaf subcircuits are known as devices and higher-level subcircuits are known as modules. Each subcircuit is represented by a dependency graph. The␣dependency graph expresses electrical dependencies of circuit parameters on a selected set of design parameters. The dependency graph of the analog IP is constructed, in a hierarchical bottom-up approach, by merging graphs of children devices and modules. The graph is converted to a directed acyclic graph (DAG) by detecting and removing existing directed cycles. The resulting DAG is the design plan for the analog IP. Upon construction, the DAG is executed, in a top-down approach, to compute the DC operating point and the dimensions of the transistors. The computed DC operating point is compared to a DC simulation to ensure its correctness. The proposed methodology has been successfully applied to size and bias two analog IPs: a single-ended two-stage operational amplifier and a␣differential cascode current-mode integrator. The results prove the efficiency and accuracy of the proposed methodology.
KeywordsAnalog EDA Hierarchical knowledge-based synthesis Design reuse DC analysis Dependency analysis
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The authors would like to thank Prof. Jacky Porte and Dr. Dimitri Galayko for valuable discussions.
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