Analog Integrated Circuits and Signal Processing

, Volume 49, Issue 2, pp 107–114 | Cite as

Design of low noise charge amplifier in sub-micron technology for fast shaping time

  • Paweł Gryboś
  • Marek Idzik
  • Andrzej Skoczeń


A discussion of the noise optimisation of the fast charge sensitive amplifier (CSA) for imaging systems using highly segmented semiconductor detectors is presented. In such systems a limited power dissipation per single channel is available while a good noise performance and a fast signal processing time are required. This paper describes the CSA noise optimisation for several CMOS technology generations with the minimum transistor gate length ranging from 0.13μm to 0.8μm and for a detector capacitance in the range from 0.5 pF to 12 pF. In a well-designed CSA, followed by a fast shaper stage, an equivalent noise charge (ENC) is dominated by the thermal noise of an input MOS transistor. In the applications considered the input transistor usually works in a moderate inversion region where no simple formula for the noise performance exists. Our analyses are made using a simplified EKV model and are compared with HSPICE simulations using BSIM3v3 models. We show several novel aspects of the noise optimisation of the CSA regarding the optimum transistor width and the sensitivity of the ENC to this width.


Charge amplifier Noise Moderate inversion 


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Copyright information

© Springer Science + Business Media, LLC 2006

Authors and Affiliations

  1. 1.Faculty of Electrical Engineering, Automatics, Computer Science and ElectronicsAGH University of Science and TechnologyPoland
  2. 2.Faculty of Physics and Applied Computer ScienceAGH University of Science and TechnologyPoland

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