Design and Performance of 155 Mbps Clock/Data Recovery Circuits on Heavy Loaded PLDs
Abstract
This paper discusses the design and performance of all-digital clock and data recovery mechanisms integrated in low-cost PLDs. Two designs have been explored and analyzed, using data sampling systems with phase detection and decision logic to select either the most appropriate sample as the recovered data or the most appropriate phase as the recovered clock. These mechanisms have been implemented in low cost PLDs from two major manufacturers. These PLDs have been further heavily loaded with typical communications functions, and the performance of the clock/data recovery circuits has been analyzed. The results show that different architectures behave differently, and that internal noise can significantly impair the performance of the circuit for high operating frequencies. This poses large difficulties to the re-usage of these blocks as generic virtual components. Nevertheless their overall performance typically exceeds regular telecommunications requirements.
Key Words
clock and data recovery synchronization PLDs oversampling clock recoveryPreview
Unable to display preview. Download preview PDF.
References
- 1.T. Hsu and B. Shied, “An all-digital phase-locked loop (ADPLL)-based clock recovery circuit.” IEEE Journal of Solid-State Circuits, vol. 34, no. 8, pp. 1063–1073, 1999.CrossRefGoogle Scholar
- 2.K. Lee, S. Kim, G. Ahn, and D. Jeong, “A CMOS serial link for fully duplexed data communications.” IEEE Journal of Solid-State Circuits, vol. 30, no. 4, pp. 353–364, 1995.CrossRefGoogle Scholar
- 3.Xilinx Inc., “Using the virtex delay-locked loop.” Advanced Application Note, Version 1.31, 21, 1998.Google Scholar
- 4.Altera Corporation, “Using the ClockLock & ClockBoost features in APEX devices.” Application Note 115, 1999.Google Scholar
- 5.C. Yang, R. Farjad-Rad, and M. Horowitz, “A 0.5 μ m CMOS 4.0Gbit/s serial link transceiver with data recovery using oversampling.” IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 713–722, 1998.CrossRefGoogle Scholar
- 6.Roland E. Best, Phase-Locked Loops, Design, Simulation & Applications, 3rd edition. McGraw-Hill, New York, 1997.Google Scholar
- 7.I. Brynjolfson and Z. Zilic, “Dynamic clock management for low power applications in FPGAs,” in Proc. Custom Integrated Circuits Conference, 2000.Google Scholar
- 8.Jin-Ku Kang, “Performance analysis of oversampling data recovery circuit,” IEIC Trans. Fundamentals, vol. E82-A, no. 6, 1999.Google Scholar