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Computational models in microfluidic bubble logic

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Abstract

The recent advancements in \(bubble\, logic\) computation based on two-phase microfluidics bring into light the possibility that the use of bubbles in microfluidic devices can carry on-chip process control. In this paper, four computational models implementing two different AND–OR logic gates, one logic NOT, and a Flip-Flop are presented. More specifically, the numerical approach used combines the Navier–Stokes equation with the phase-field method. All reported models are based on generally accepted and already experimentally tested chip designs. A parametric T-junction model has been designed to be connected to the logic gate models as a droplet generator. The wider framework on the logic gate behavior in different operating conditions reveals the relevance of these models in the microfluidics chip design. Moreover, the advantage of using a simulation platform for the investigation of electrical circuits equivalent of microfluidic processes is illustrated. In this context, the focus of this paper was not only the definition of CFD models of logic gates, but the attempt to establish a workbench easily accessible for the study of the two-phase microfluidic processes.

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Acknowledgments

This work was partially supported by MIUR in the framework of the PRIN09 (2011–2013) for the research project entitled “Integration of Strategies for an Innovative Control of Microfluidics Systems and Applicative Validity”.

Author information

Correspondence to Maide Bucolo.

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Supplementary material 1 (wmv 2036 KB)

Supplementary material 2 (wmv 2067 KB)

Supplementary material 3 (wmv 3294 KB)

Supplementary material 4 (wmv 544 KB)

Supplementary material 5 (wmv 512 KB)

Supplementary material 6 (wmv 4061 KB)

Supplementary material 7 (wmv 2724 KB)

Supplementary material 8 (wmv 161 KB)

Supplementary material 9 (wmv 176 KB)

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Anandan, P., Gagliano, S. & Bucolo, M. Computational models in microfluidic bubble logic. Microfluid Nanofluid 18, 305–321 (2015). https://doi.org/10.1007/s10404-014-1434-7

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Keywords

  • Phase-field method
  • T-junction
  • AND–OR gate
  • NOT gate
  • Memory circuit