Software & Systems Modeling

, Volume 14, Issue 1, pp 343–363 | Cite as

Formal verification and validation of embedded systems: the UML-based MADES approach

  • Luciano Baresi
  • Gundula Blohm
  • Dimitrios S. Kolovos
  • Nicholas Matragkas
  • Alfredo Motta
  • Richard F. Paige
  • Alek Radjenovic
  • Matteo RossiEmail author
Special Section Paper


Formal verification and validation activities from the early development phases can foster system consistency, correctness, and integrity, but they are often hard to carry out as most designers do not have the necessary background. To address this difficulty, a possible approach is to allow engineers to continue using familiar notations and tools, while verification and validation are performed on demand, automatically, and transparently. In this paper we describe how the problem of making formal verification and validation tasks more designer-friendly is tackled by the MADES approach. Our solution is based on a tool chain that is built atop mature, popular, and widespread technologies. The paper focuses on the verification and closed-loop simulation (validation) aspects of the approach and shows how it can be applied to significant embedded software systems.


Model-driven development Verification Closed-loop simulation MARTE Embedded systems 



This research was supported by the Seventh Framework Program (FP7/2007–2013) of the European Community, project MADES (248864), and by the Programme IDEAS-ERC, project SMScom (227977).


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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Luciano Baresi
    • 1
  • Gundula Blohm
    • 2
  • Dimitrios S. Kolovos
    • 3
  • Nicholas Matragkas
    • 3
  • Alfredo Motta
    • 1
  • Richard F. Paige
    • 3
  • Alek Radjenovic
    • 3
  • Matteo Rossi
    • 1
    Email author
  1. 1.Dipartimento di Elettronica Informazione e BioingegneriaPolitecnico di MilanoMilanItaly
  2. 2.CassidianUlmGermany
  3. 3.Department of Computer ScienceUniversity of YorkYorkUK

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