Advertisement

Mathematical Programming

, Volume 121, Issue 2, pp 201–220 | Cite as

Optimal wire ordering and spacing in low power semiconductor design

  • Peter Gritzmann
  • Michael Ritter
  • Paul Zuber
FULL LENGTH PAPER Series A

Abstract

A key issue for high integration circuit design in the semiconductor industry are power constraints that stem from the need for heat removal and reliability or battery lifetime limitations. As the power consumption depends heavily on the capacitances between adjacent wires, determining the optimal ordering and spacing of parallel wires is an important issue in the design of low power chips. As it turns out, optimal wire spacing is a convex optimization problem, whereas the optimal wire ordering is combinatorial in nature, containing (a special class of) the Minimum Hamilton Path problem. While the latter is \({\mathcal{NP}}\)-hard in general, the present paper provides an \({\mathcal{O}{(N \log N)}}\) algorithm that solves the coupled ordering and spacing problem for N parallel wires to optimality.

Keywords

Optimal wire placement Convex programming Combinatorial optimization Hamilton path 

Mathematics Subject Classification (2000)

90C27 90C25 90C90 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Burkard R.E.: Special cases of travelling salesman problems and heuristics. Acta Mathematicae Applicatae Sinica (English Series) 6(3), 273–288 (1990)MATHCrossRefMathSciNetGoogle Scholar
  2. 2.
    Burkard R.E., Çela E., Rote G., Woeginger G.J.: The quadratic assignment problem with a monotone anti-Monge and a symmetric Toeplitz matrix: easy and hard cases. Math. Program. 82, 125–158 (1998)Google Scholar
  3. 3.
    Burkard R.E., Deineko V.G., van Dal R., van der Veen J.A.A., Woeginger G.J.: Well-solvable special cases of the traveling salesman problem: a survey. SIAM Rev. 40(3), 496–546 (1998)MATHCrossRefMathSciNetGoogle Scholar
  4. 4.
    Coz Y.L.L., Iverson R.B.: A stochastic algorithm for high speed capacitance extraction in integrated circuits. Solid State Electron. 35, 1005–1012 (1992)CrossRefGoogle Scholar
  5. 5.
    Gilmore P.C., Lawler E.L., Shmoys D.B.: Well-solved special cases. In: Lawler, E.L., Lenstra, J.K., Rinnooy Kan, A.H.G., Shmoys, D.B. (eds) The Traveling Salesman Problem, A Guided Tour of Combinatorial Optimization, chap. 4, pp. 87–143. Wiley, London (1985)Google Scholar
  6. 6.
    Groeneveld P.: Wire ordering for detailed routing. Des. Test Comput. 6, 6–17 (1989)CrossRefGoogle Scholar
  7. 7.
    Macchiarulo, L., Macii, E., Poncino, M.: Low-energy encoding for deep-submicron address buses. In: Proceedings of the 2001 International Symposium on Low Power Electronics and Design, pp. 176–181 (2001)Google Scholar
  8. 8.
    Macchiarulo, L., Macii, E., Poncino, M.: Wire placement for crosstalk energy minimization in address buses. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 2002, pp. 158–162 (2002)Google Scholar
  9. 9.
    Macii, E., Poncino, M., Salerno, S.: Combining wire swapping and spacing for low-power deep-submicron buses. In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI, pp. 198–202 (2003)Google Scholar
  10. 10.
    Michaely S., Moiseev K., Kolodny A.: Optimal bus sizing in migration of processor design. IEEE Trans Circuits Syst Part 1 Regular Papers 53(5), 1089–1100 (2006)CrossRefGoogle Scholar
  11. 11.
    Moiseev, K., Wimer, S., Kolodny, A.: Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. In: Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 329–332 (2006)Google Scholar
  12. 12.
    Semiconductor Industry Association: International Technology Roadmap for Semiconductors (ITRS): 2005 Edition (2005). URL http://www.itrs.net/Links/2005ITRS/Home2005.htm
  13. 13.
    Supnick F.: Extreme Hamiltonian lines. Ann. Math. 66, 179–201 (1957)CrossRefMathSciNetGoogle Scholar
  14. 14.
    Vygen J.: Near-optimum global routing with coupling, delay bounds, and power consumption. In: Bienstock, D., Nemhauser, G. (eds) Integer Programming and Combinatorial Optimization, Lecture Notes in Computer Science, vol. 3064, pp. 308–324. Springer, Heidelberg (2004)Google Scholar
  15. 15.
    Windschiegl A., Zuber P., Stechele W.: Exploiting metal layer characteristics for low-power routing. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, Lecture Notes in Computer Science, vol. 2451, pp. 55–64. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  16. 16.
    Woeginger G.J.: Computational problems without computation. Nieuw Archief voor Wiskunde 5/4(2), 140–147 (2003)Google Scholar
  17. 17.
    Yim, J., Kyung, C.: Reducing cross-coupling among interconnect wires in deep-submicron datapath design. In: Proceedings of the 36th ACM/IEEE Conference on Design automation, pp. 485–490 (1999)Google Scholar
  18. 18.
    Zuber, P.: Wire topology optimisation for low power CMOS. Ph.D. thesis, TU München (2007). URL http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:bvb:91-dis s-20070802-618152-1-6
  19. 19.
    Zuber, P., Gritzmann, P., Ritter, M., Stechele, W.: The optimal wire order for low power CMOS. In: Integrated Circuit and System Design, Lecture Notes in Computer Science, vol. 3728, pp. 664–683. Springer, Heidelberg (2005)Google Scholar

Copyright information

© Springer-Verlag 2008

Authors and Affiliations

  1. 1.Department of MathematicsTechnische Universität MünchenMünchenGermany
  2. 2.Department of Electrical Engineering and Information TechnologyTechnische Universität MünchenMünchenGermany
  3. 3.Interuniversity Microelectronics Centre (IMEC), Nomadic Embedded SystemsLeuvenBelgium

Personalised recommendations