Silicon neuron: digital hardware implementation of the quartic model
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This paper presents an FPGA implementation of the quartic neuron model. This approach uses digital computation to emulate individual neuron behavior. We implemented the neuron model using fixed-point arithmetic operation. The neuron model’s computations are performed in arithmetic pipelines. It was designed in VHDL language and simulated prior to mapping in the FPGA. We show that the proposed FPGA implementation of the quartic neuron model can emulate the electrophysiological activities in various types of cortical neurons and is capable of producing a variety of different behaviors, with diversity similar to that of neuronal cells. The neuron family of this digital neuron can be modified by appropriately adjusting the neuron model’s parameters.
KeywordsSilicon neuron Neuromorphic engineering FPGA Cortical neuron Quartic model
This work was supported by the European Union’s Seventh Framework Programme (ICT-FET FP7/2007-2013, FET Young Explorers scheme) under Grant agreement no 284772 BRAIN BOW (http://www.brainbowproject.eu).
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