Program slicing for VHDL
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Hardware description languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in design, simulation, testing, and formal verification. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. Slicing is fundamentally based on data and control dependences between program points. However, program slicing algorithms have traditionally been designed for sequential languages, and the presence of concurrent constructs such as those found in HDLs complicates slicing considerably. In this paper, we develop the concepts needed for slicing VHDL. The techniques extend readily to other HDLs such as Verilog. Our techniques are based on a slicing-oriented VHDL execution semantics that augments traditional dependences with inter-procedural dependences between VHDL processes. Based on these concepts, we have developed an automatic VHDL slicing tool composed of a traditional slicer and a front-end that captures VHDL simulation semantics. This paper discusses our techniques for VHDL slicing, the slicer tool, and slicing applications in design, simulation, testing, and formal verification of VHDL programs. A particularly important application of HDL slicing is source code reduction leading to reduced state spaces for model checking, and we also present empirical results for this.
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