From high-level modeling toward efficient and trustworthy circuits

  • Fadi A. Zaraket
  • Mohamad JaberEmail author
  • Mohamad Noureddine
  • Yliès Falcone
Regular Paper


Behavior–interaction–priority (BIP) is a layered embedded system design and verification framework that provides separation of functionality, synchronization, and priority concerns to simplify system design and to establish correctness by construction. BIP framework comes with a runtime engine and a suite of verification tools that use D-Finder and NuSMV as model-checkers. In this paper, we provide a method and a supporting tool that take a BIP system and a set of invariants and compute a reduced sequential circuit with a system-specific scheduler and a designated output that is \(\mathtt {true}\) when the invariants hold. Our method uses ABC, a sequential circuit synthesis and verification framework, to (1) generate an efficient circuit implementation of the system that can be readily translated into FPGA or ASIC implementations and to (2) verify the system and debug it in case a counterexample is found. Moreover, we generate a concurrent C implementation of the circuit that can be directly used for runtime verification. We evaluated our method with two benchmark systems, and our results show that, compared to existing techniques, our method is faster and scales to larger sizes.


Component-based design Correct-by-construction FPGA Verification 


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Copyright information

© Springer-Verlag GmbH Germany 2017

Authors and Affiliations

  • Fadi A. Zaraket
    • 1
  • Mohamad Jaber
    • 1
    Email author
  • Mohamad Noureddine
    • 2
  • Yliès Falcone
    • 3
  1. 1.American University of BeirutBeirutLebanon
  2. 2.Performability Engineering Research GroupUniversity of Illinois at Urbana-ChampaignUrbanaUSA
  3. 3.Laboratoire d’Informatique de GrenobleUniv. Grenoble-Alpes, InriaGrenobleFrance

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