A blueprint for system-level performance modeling of software-intensive embedded systems

  • Martijn Hendriks
  • Twan Basten
  • Jacques Verriet
  • Marco Brassé
  • Lou Somers
Regular Paper

Abstract

Exploration of design alternatives and estimation of their key performance metrics such as latency and energy consumption is essential for making the proper design decisions in the early phases of system development. Often, high-level models of the dynamic behavior of the system are used for the analysis of design alternatives. Our work presents a blueprint for building efficient and re-usable models for this purpose. It builds on the well-known Y-chart pattern in that it gives more structure for the proper modeling of interaction on shared resources that plays a prominent role in software-intensive embedded systems. We show how the blueprint can be used to model a small yet illustrative example system with the Uppaal tool, and with the Java general-purpose programming language, and reflect on their respective strengths and weaknesses. The Java-based approach has resulted in a very flexible and fast discrete-event simulator with many re-usable components. It currently is used by TNO-ESI and Océ-Technologies B.V. for early model-based performance analysis that supports the design process for professional printing systems.

Keywords

Embedded system System-level modeling Performance analysis Simulation Design space exploration 

Notes

Acknowledgments

We thank the anonymous reviewers for their valuable comments that helped us to improve the paper.

References

  1. 1.
    Alur, R., Dill, D.L.: A theory of timed automata. Theor. Comput. Sci. 126(2), 183–235 (1994)CrossRefMathSciNetMATHGoogle Scholar
  2. 2.
    Alur, R., et al.: The algorithmic analysis of hybrid systems. Theor. Comput. Sci. 138(1), 3–34 (1995)CrossRefMathSciNetMATHGoogle Scholar
  3. 3.
    Balarin, F., et al.: Hardware–Software Co-design of Embedded Systems: The POLIS Approach. Kluwer, Dordrecht (1997)CrossRefMATHGoogle Scholar
  4. 4.
    Basten, T., et al.: Model-driven design-space exploration for embedded systems: the Octopus toolset. In: ISoLA 2010, volume 6415 of LNCS. Springer (2010)Google Scholar
  5. 5.
    Basten, T., et al.: Model-driven design-space exploration for software-intensive embedded systems. In: Model-Based Design of Adaptive Embedded Systems, volume 22 of Embedded Systems, pp. 189–244. Springer, New York (2013)Google Scholar
  6. 6.
    Becker, S., Koziolek, H., Reussner, R.: Model-based performance prediction with the palladio component model. In: Proceedings of the 6th International Workshop on Software and Performance, WOSP ’07, New York, NY, USA. ACM (2007)Google Scholar
  7. 7.
    Behrmann, G., David, A., Larsen, K.G.: A tutorial on Uppaal. In: SFM, volume 3185 of Lecture Notes in Computer Science. Springer (2004)Google Scholar
  8. 8.
    Behrmann, G., et al.: Uppaal 4.0. In: Proceedings of the 3rd International Conference on the Quantitative Evaluation of Systems, QEST ’06. IEEE Computer Society (2006)Google Scholar
  9. 9.
    Berthomieu, B., Diaz, M.: Modeling and verification of time dependent systems using time petri nets. IEEE Trans. Softw. Eng. 17(3), 259–273 (1991)CrossRefMathSciNetGoogle Scholar
  10. 10.
    Bloch, J.: Effective Java, 2nd edn. Addison-Wesley, Boston (2008)Google Scholar
  11. 11.
    Brekling, A., Hansen, M.R., Madsen, J.: Models and formal verification of multiprocessor system-on-chips. J. Logic Algebr. Progr. 77(1–2), 1–19 (2008)Google Scholar
  12. 12.
    Brekling, A., Hansen, M.R., Madsen, J.: Moves: a framework for modelling and verifying embedded systems. In: Microelectronics (ICM), 2009 International Conference (2009)Google Scholar
  13. 13.
    Cassez, F., Larsen, K.G.: The impressive power of stopwatches. In: Proceedings of the 11th International Conference on Concurrency Theory, CONCUR ’00. Springer (2000)Google Scholar
  14. 14.
    Cassidy, A.S., Paul, J.M., Thomas, D.E.: Layered, multi-threaded, high-level performance design. In: Design, Automation and Test in Europe Conference and Exhibition (2003)Google Scholar
  15. 15.
    David, A., Illum, J., Larsen, K.G., Skou, A.: Model-based framework for schedulability analysis using Uppaal 4.1. In: Model-Based Design for Embedded Systems (2009)Google Scholar
  16. 16.
    David, A., Larsen, K.G., Legay, A., Mikučionis, M.: Schedulability of Herschel–Planck revisited using statistical model checking. In: Leveraging Applications of Formal Methods, Verification and Validation. Applications and Case Studies, volume 7610 of Lecture Notes in Computer Science. Springer, Berlin, Heidelberg (2012)Google Scholar
  17. 17.
    David, A., et al.: Statistical model checking for networks of priced timed automata. In: Proceedings of the 9th international conference on formal modeling and analysis of timed systems, FORMATS’11. Springer, Berlin, Heidelberg (2011)Google Scholar
  18. 18.
    Ebert, C., Jones, C.: Embedded software: facts, figures, and future. Computer 42(4), 42–52 (2009)CrossRefGoogle Scholar
  19. 19.
    Gamma, E., Helm, R., Johnson, R., Vlissides, J.: Design Patterns: Elements of Reusable Object-Oriented Software, 1st edn. Addison-Wesley Professional, Boston (1994)Google Scholar
  20. 20.
    Gerstlauer, A., Chakravarty, S., Kathuria, M., Razaghi, P.: Abstract system-level models for early performance and power exploration. In: 17th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE (2012)Google Scholar
  21. 21.
    Gerstlauer, A., Yu, Haobo, Gajski, D.D.: Rtos modeling for system level design. In: Design, Automation and Test in Europe Conference and Exhibition (2003)Google Scholar
  22. 22.
    Goetz, B., et al.: Java Concurrency in Practice, 1st edn. Addison-Wesley, Boston (2006)Google Scholar
  23. 23.
    Grassi, V., Mirandola, R., Sabetta, A.: From design to analysis models: a kernel language for performance and reliability analysis of component-based systems. In: Proceedings of the 5th International Workshop on Software and Performance (WOSP ’05), New York, NY, USA. ACM (2005)Google Scholar
  24. 24.
    Hendriks, M., Geilen, M., Basten, T.: Pareto analysis with uncertainty. In: Proceedings of the 2011 IFIP 9th International Conference on Embedded and Ubiquitous Computing, EUC ’11. IEEE Computer Society (2011)Google Scholar
  25. 25.
    Hendriks, M., Vaandrager, F.W.: Reconstructing critical paths from execution traces. In: IEEE 15th International Conference on Computational Science and Engineering (CSE). IEEE Computer Society (2012)Google Scholar
  26. 26.
    IBM tells story behind Chevy Volt design. http://www.eetimes.com/document.asp?doc_id=1259444 (2011). Accessed 26 Aug 2014
  27. 27.
    Igna, G.: Performance analysis of real-time task systems using timed automata. Ph.D. thesis, Radboud University Nijmegen (2013)Google Scholar
  28. 28.
    Jensen, K., Kristensen, L.M., Wells, L.: Coloured petri nets and cpn tools for modelling and validation of concurrent systems. STTT 9(3–4), 213–254 (2007)Google Scholar
  29. 29.
    Kienhuis, B., Deprettere, E., Vissers, K., van der Wolf, P.: An approach for quantitative analysis of application-specific dataflow architectures. In: Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP ’97. IEEE Computer Society (1997)Google Scholar
  30. 30.
    Lapalme, J., et al.: Y-chart based system design: a discussion on approaches. In: Nouvelles approches pour la conception d’outils CAO pour le domaine des systems embarqués (2009)Google Scholar
  31. 31.
    Le Moigne, R., Pasquier, O., Calvez, J. P.: A generic rtos model for real-time systems simulation with SystemC. In: Design, Automation and Test in Europe, vol. 3 (2004)Google Scholar
  32. 32.
    Madsen, J., Virk, K., Gonzales, M.: Abstract rtos modeling for multiprocessor system-on-chip. In: System-on-Chip, 2003. Proceedings. International Symposium (2003)Google Scholar
  33. 33.
    Mahadevan, S., Virk, K., Madsen, J.: A SystemC-based framework for multiprocessor systems-on-chip modelling. Des. Autom. Embed. Syst. 11(4), 285–311 (2007)CrossRefGoogle Scholar
  34. 34.
    Martens, A., Koziolek, H., Becker, S., Reussner, R.: Automatically improve software architecture models for performance, reliability, and cost using evolutionary algorithms. In: Proceedings of the First Joint WOSP/SIPEW International Conference on Performance Engineering, WOSP/SIPEW 2010. ACM (2010)Google Scholar
  35. 35.
    Meffert, K., et al.: JGAP—Java genetic algorithms and genetic programming package. http://jgap.sourceforge.net/. Accessed 26 Aug 2014
  36. 36.
    Panerati, J., Beltrame, G.: A comparative evaluation of multi-objective exploration algorithms for high-level design. ACM Trans. Des. Autom. Electron. Syst. 19(2), 1–22 (2014) Google Scholar
  37. 37.
    Paul, J.M., Thomas, D.E., Cassidy, A.S.: High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. ACM Trans. Des. Autom. Electron. Syst. 10(3), 431–461 (2005)CrossRefGoogle Scholar
  38. 38.
    Paul, J.M., et al.: Schedulers as model-based design elements in programmable heterogeneous multiprocessors. In: Design Automation Conference, 2003. Proceedings (2003)Google Scholar
  39. 39.
    Pimentel, A.D., Erbas, C., Polstra, S.: A systematic approach to exploring embedded system architectures at multiple abstraction levels. Comput. IEEE Trans. 55(2), 99–112 (2006)CrossRefGoogle Scholar
  40. 40.
    Smith, C.U.: Introduction to software performance engineering: origins and outstanding problems. In: Formal Methods for Performance Evaluation, volume 4486 of Lecture Notes in Computer Science. Springer, Berlin, Heidelberg (2007)Google Scholar
  41. 41.
    SPE Economics. http://www.perfeng.com/econ.htm. Accessed 26 Aug 2014
  42. 42.
    SpecC. http://www.cecs.uci.edu/~specc/. Accessed 26 Aug 2014
  43. 43.
    Enhanced Intel SpeedStep Technology for the Intel Pentium M Processor. http://download.intel.com/design/network/papers/30117401.pdf. Accessed 26 Aug 2014
  44. 44.
    System-C. http://www.systemc.org/home/. Accessed 26 Aug 2014
  45. 45.
    Theelen, B.D.: Performance modelling for system-level design. Ph.D. thesis, Eindhoven University of Technology (2004)Google Scholar
  46. 46.
    Trcka, N., Voorhoeve, M., Basten, T.: Parameterized timed partial orders with resources: formal definition and semantics. Technical Report ESR-2010-01, Eindhoven University of Technology, Department of Electrical Engineering, Eindhoven, The Netherlands (2010)Google Scholar
  47. 47.
    Trcka, N. et al.: Integrated model-driven design-space exploration for embedded systems. In: International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. IEEE Computer Society (2011)Google Scholar
  48. 48.
    van der Putten, P.H.A., Voeten, J.P.M.: Specification of reactive hardware/software systems. Ph.D. thesis, Eindhoven University of Technology (1997)Google Scholar
  49. 49.
    Zitzler, E., Laumanns, M., Thiele, L.: SPEA2: improving the strength Pareto evolutionary algorithm for multiobjective optimization. In: Evolutionary Methods for Design, Optimisation and Control with Application to Industrial Problems (EUROGEN 2001). International Center for Numerical Methods in Engineering (CIMNE) (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2014

Authors and Affiliations

  • Martijn Hendriks
    • 1
  • Twan Basten
    • 1
    • 2
  • Jacques Verriet
    • 1
  • Marco Brassé
    • 3
  • Lou Somers
    • 2
    • 3
  1. 1.Embedded Systems Innovation by TNOEindhovenThe Netherlands
  2. 2.Eindhoven University of TechnologyEindhovenThe Netherlands
  3. 3.Océ-Technologies B.V.VenloThe Netherlands

Personalised recommendations