A bit too precise? Verification of quantized digital filters

  • Arlen Cox
  • Sriram Sankaranarayanan
  • Bor-Yuh Evan Chang
TACAS 2012

Abstract

Fixed-point digital filters are simple yet ubiquitous components of a wide variety of digital processing and control systems. Common errors in fixed-point filters include arithmetic round-off (truncation) errors, overflows and the presence of limit cycles. These errors can potentially compromise the correctness of the system as a whole. Traditionally, digital filters have been verified using a combination of design techniques from control theory and extensive testing. In this paper, we examine the use of formal verification techniques as part of the design flow for fixed-point digital filters. We study two classes of verification techniques involving bit-precise analysis and real-valued error approximations, respectively. We empirically evaluate several variants of these two fundamental approaches for verifying fixed-point implementations of digital filters. We design our comparison to reveal the best possible approach towards verifying real-world designs of infinite impulse response (IIR) digital filters. Our study compares the strengths and weaknesses of different verification techniques for digital filters and suggests efficient approaches using modern satisfiability-modulo-theories solvers (SMT) and hardware model checkers. This manuscript extends our previous work evaluating bounded verification, where a limited number of iterations of the system are explored, with unbounded verification, where an unlimited number of iterations of the system are considered. Doing so allows us to evaluate techniques that can prove the correctness of fixed-point digital filter implementations.

Keywords

Verification Bug finding Digital Filters Linear system Model checking 

References

  1. 1.
    Akbarpour, B., Tahar, S.: Error analysis of digital filters using HOL theorem proving? J. Appl. Log. 5(4), 651–666 (2007)CrossRefMATHMathSciNetGoogle Scholar
  2. 2.
    Alegre, F., Feron, E., Pande, S.: Using ellipsoidal domains to analyze control systems software. CoRR, abs/0909.1977 (2009)Google Scholar
  3. 3.
    Barrett, C., Deters, M., de Moura, L., Oliveras, A., Stump, A.: 6 years of SMT-COMP. J. Autom. Reason. 50(3):243–277 (2013)Google Scholar
  4. 4.
    Biere, A.: The AIGER And-Inverter Graph (AIG) Format Version 20071012 (2007)Google Scholar
  5. 5.
    Biere, A., Heljanko, K.: Hardware model checking competition. In: FMCAD (2011)Google Scholar
  6. 6.
    Blanchet, B., Cousot, P., Cousot, R., Feret, J., Mauborgne, L., Miné, A., Monniaux, D., Rival, X.: Design and implementation of a special-purpose static program analyzer for safety-critical real-time embedded software (invited chapter). In: The Essence of Computation: Complexity, Analysis, Transformation. Essays Dedicated to Neil D. Jones, volume 2566 of LNCS, pp. 85–108. Springer, Berlin (2005)Google Scholar
  7. 7.
    Bradley, A.R.: SAT-based model checking without unrolling. In: Jhala, R., Schmidt, D. (eds.) Verification, Model Checking, and Abstract Interpretation (VMCAI), vol. 6538, pp. 70–87. Springer, Berlin (2011)Google Scholar
  8. 8.
    Brayton, R.K., Mishchenko, A.: ABC: an academic industrial-strength verification tool. In: Computer-Aided Verification (CAV), pp. 24–40 (2010)Google Scholar
  9. 9.
    Brillout, A., Kroening, D., Wahl, T.: Mixed abstractions for floating-point arithmetic. In: Formal Methods in Computer Aided Design (FMCAD), pp. 69–76 (2009)Google Scholar
  10. 10.
    Clarke, E., Biere, A., Raimi, R., Zhu, Y.: Bounded model checking using satisfiability solving. Form. Methods Syst. Des. 19(1), 7–34 (2001)CrossRefMATHGoogle Scholar
  11. 11.
    Cox, A., Sankaranarayanan, S., Chang, B.-Y.E.: A bit too precise? Bounded verification of quantized digital filters. In: Tools and Algorithms for the Construction and Analysis of Systems (TACAS), pp. 33–47 (2012)Google Scholar
  12. 12.
    Craig, W.: Linear reasoning. A new form of the Herbrand-Gentzen theorem. J. Symb. Log. 22(3), 250–268 (1957)CrossRefMATHMathSciNetGoogle Scholar
  13. 13.
    de Figueiredo, L.H., Stolfi, J.: Self-validated numerical methods and applications. In: Brazilian Mathematics Colloquium monograph. IMPA, Rio de Janeiro, Brazil (1997)Google Scholar
  14. 14.
    De Moura, L., Bjørner, N.: Z3: an efficient SMT solver. In: Tools and Algorithms for the Construction and Analysis of Systems (TACAS), pp. 337–340 (2008)Google Scholar
  15. 15.
    Een, N., Mishchenko, A., Brayton, R.: Efficient implementation of property directed reachability. In: Formal Methods in Computer Aided Design (FMCAD), pp. 125–134. FMCAD Inc (2011)Google Scholar
  16. 16.
    Fang, C., Rutenbar, R., Chen, T.: Fast, accurate static analysis for fixed-point finite-precision effects in DSP designs. In: International Conference on Computer-Aided Design (ICCAD), pp. 275–282 (2003)Google Scholar
  17. 17.
    Feret, J.: Static analysis of digital filters. In: Programming Languages and Systems 2986, 33–48 (2004)Google Scholar
  18. 18.
    Fränzle, M., Herde, C., Ratschan, S., Schubert, T., Teige, T.: Efficient solving of large non-linear arithmetic constraint systems with complex Boolean structure. JSAT 1(3–4), 209–236 (2007)Google Scholar
  19. 19.
    Goubault, E., Putot, S.: Static analysis of finite precision computations. In: Verification, Model Checking, and Abstract Interpretation (VMCAI), pp. 232–247 (2011)Google Scholar
  20. 20.
    Hoder, K., Bjørner, N.: Generalized property directed reachability. In: Cimatti, A., Sebastiani, R. (eds.) Theory and Applications of Satisfiability Testing (SAT), vol. 7317, pp. 157–171. Springer, Berlin (2012)Google Scholar
  21. 21.
    Kinsman, A.B., Nicolici, N.: Finite precision bit-width allocation using SAT-modulo theory. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE ’09, p. 11061111. European Design and Automation Association (2009)Google Scholar
  22. 22.
    Lee, D., Gaffar, A., Cheung, R., Mencer, O., Luk, W., Constantinides, G.: Accuracy-guaranteed bit-width optimization. IEEE Trans. CAD Integr. Circuits Syst. 25(10), 1990–2000 (2006)CrossRefGoogle Scholar
  23. 23.
    McMillan, K.L.: Interpolation and SAT-based model checking. In: Computer-Aided Verification (CAV), pp. 1–13 (2003)Google Scholar
  24. 24.
    Monniaux, D.: Compositional analysis of floating-point linear numerical filters. In: Computer-Aided Verification (CAV), vol. 3576, pp. 199–212 (2005)Google Scholar
  25. 25.
    Monniaux, D.: On using floating-point computations to help an exact linear arithmetic decision procedure. In: Computer-Aided Verification (CAV), pp. 570–583 (2009)Google Scholar
  26. 26.
    Oppenheim, A.V., Willsky, A.S., Nawab, S.H.: Signals & Systems, 2nd edn. Prentice Hall, Englewood Cliffs (1997)Google Scholar
  27. 27.
    Pang, Y., Radecka, K., Zilic, Z.: Optimization of imprecise circuits represented by taylor series and real-valued polynomials. IEEE Trans. CAD Integr. Circuits Syst. 29(8), 1177–1190 (2010)CrossRefGoogle Scholar
  28. 28.
    Pang, Y., Radecka, K., Zilic, Z.: An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. In: Asia South Pacific Design Automation Conference (ASP-DAC), pp. 455–460 (2011) Google Scholar
  29. 29.
    Smith, J.O.: Introduction to Digital Filters: With Audio Applications. W3K Publishing. http://books.w3k.org/, ISBN 978-0-9745607-1-7 (2007)
  30. 30.
    Sung, W., Kum, K.: Simulation-based word-length optimization method for fixed-point digital signal processing systems. IEEE Trans. Signal Process. 43(12), 3087–3090 (1995)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Arlen Cox
    • 1
  • Sriram Sankaranarayanan
    • 1
  • Bor-Yuh Evan Chang
    • 1
  1. 1.University of Colorado BoulderBoulderUSA

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