System-on-chip design by proof-based refinement

Regular Paper


Systems-on-chip (SoCs) and SoC architectures provide a collection of challenging problems related to specification, modelling techniques, security issues and structuring questions. We describe a design methodology integrating the event B method and characterized by the incremental and proof-controlled construction of SoC models. The essence of the methodology is the refinement of models, starting from system requirements and producing event B models for characterizing the system under development. The refinement is a unifying concept that ensures the consistency of the different models produced and our contribution is an illustration through a case study, namely a system for measuring the parameters of audio/video quality in the digital video broadcasting (DVB) set of digital TV standards. The first part is the derivation of an architecture of parameters from the document ETSI TR 101 290 and the validation of the architecture using invariants of B models. The second part is the proposal of B models of the SystemC scheduler and an instantiation of these abstract models of the simulation semantics by parameters of the SystemC codes automatically translated from the B models of the DVB system. Finally, the third part relies upon a proof-based methodology for deriving an operational semantics of a given system that is expressed by an event B model including invariant properties.


Event B method Refinement System-on-chip Proof Formal modelling SystemC Simulation Operational semantics 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Abraham, D., Cansell, D., Ditsch, P., Méry, D., Proch, C.: The challenge of QoS for digital television services. EBU Technical Review, April 2005Google Scholar
  2. 2.
    Abraham, D., Cansell, D., Ditsch, P., Méry, D., Proch, C.: Synthesis of the QoS for digital TV services. In: IBC’05, The Netherlands (2005)Google Scholar
  3. 3.
    Abrial J.-R.: The B Book—Assigning Programs to Meanings. Cambridge University Press, London (1996) ISBN 0-521-49619-5MATHGoogle Scholar
  4. 4.
    Abrial, J.-R., Cansell, D.: Click’n’Prove: interactive proofs within set theory. In: David Basin et Burkhart Wolff (ed.) 16th International Conference on Theorem Proving in Higher Order Logics—TPHOLs’2003, Rome.Lecture notes in Computer Science, vol. 2758, pp. 1–24. Springer, Heidelberg (2003)Google Scholar
  5. 5.
    Abrial J.-R., Cansell D., Méry D.: A mechanically proved and incremental development of IEEE 1394 tree identify protocol. Formal Asp. Comput. 14(3), 215–227 (2003)CrossRefGoogle Scholar
  6. 6.
    Back R.J.R.: On correct refinement of programs. J. Comput. Syst. Sci. 23(1), 49–68 (1979)CrossRefMathSciNetGoogle Scholar
  7. 7.
    Balarin F., Chiodo M., Giusto P., Hsieh H., Jurecska A., Lavagno L., Passerone C., Sangiovanni-Vincentelli A., Sentovich E., Suzuki K., Tabbara B.: Hardware-Software Co-Design of Embedded Systems. Kluwer, Dordrecht (2000)Google Scholar
  8. 8.
    Berry G.: Esterel on hardware. Philos. Trans. R. Soc. Lond. 339, 87–104 (1992)CrossRefGoogle Scholar
  9. 9.
    Berry G., Gonthier G.: The Esterel synchronous programming language: design, semantics, implementation. Sci. Comput. Program. 19(2), 87–152 (1992)MATHCrossRefGoogle Scholar
  10. 10.
    Bjørner, D., Henson, M.C. (eds.): Logics of Specification Languages. EATCS Textbook in Computer Science. Springer, Heidelberg (2007)Google Scholar
  11. 11.
    Cansell, D., Culat, J.-F., Méry, D., Proch, C.: Derivation of SystemC code from abstract system models. In: Forum on specification & Design Languages—FDL’04, Lille, France, September 2004Google Scholar
  12. 12.
    Cansell D., Méry D.: The event-B Modelling Method: Concepts and Case Studies, pp. 33–140. Springer, Berlin (2007)Google Scholar
  13. 13.
    Cansell, D., Méry, D., Proch, C.: Projet RNRT EQUAST SP2 spécification incrémentale du système. Rapport de recherche, LORIA, October 2004Google Scholar
  14. 14.
    Cansell, D., Tanougast, C., Berviller, Y., Méry, D., Proch, C., Rabah, H., Weber, S.: Proof-based design of a microelectronic architecture for mpeg-2 bit-rate measurement. In: Forum on specification and Design Languages—FDL’03, Frankfurt, Germany, September 2003Google Scholar
  15. 15.
    Chandy K.M., Misra J.: Parallel Program Design A Foundation. Addison-Wesley, Reading (1988) ISBN 0-201-05866-9MATHGoogle Scholar
  16. 16.
    Clarke E.M., Grumberg O., Peled D.A.: Model Checking. The MIT Press, (2000)Google Scholar
  17. 17.
    ClearSy. Web site B4free set of tools for development of B models. (2004)
  18. 18.
    Cousot, P.: Verification by abstract interpretation. In: Dershowitz, N. (ed.) Proc. Int. Symp. on Verification—Theory & Practice—Honoring Zohar Manna’s 64th Birthday, pp. 243–268. Taormina, Italy, June 29–July 4 2003Google Scholar
  19. 19.
    Dijkstra E.W.: A Discipline of Programming. Prentice-Hall, Englewood Cliffs (1976)MATHGoogle Scholar
  20. 20.
    European Broadcasting Union. Digital video broadcasting (DVB)- measurement guidelines for DVB systems. Technical Report TR 101 290 v1.2.1., ETSI, 05 (2001)Google Scholar
  21. 21.
    Gawanmeh, A., Habibi, A., Tahar, S.: An executable operational semantics for SystemC using Abstract State Machines. Technical report, Concordia University, Department of Electrical and Computer Engineering, March 2005Google Scholar
  22. 22.
    Glässer U., Börger E., Müller W.: Formal definition of an abstract VHDL’93 simulator by EA-machines. In: DelgadoKloos, C., Breuer, P.T. (eds) Formal Semantics for VHDL, Kluwer, Dordrecht (1995)Google Scholar
  23. 23.
    Hardware Verification Group. Hands-on Manual to FormalCheck, Version 2.3. Concordia University, Montreal (2000)Google Scholar
  24. 24.
    Habibi A., Tahar S.: On the transformation of systemc to asml using abstract interpretation. Electron. Notes Theor. Comput. Sci. 131, 39–49 (2005)CrossRefGoogle Scholar
  25. 25.
    Holmström, S., Sere, K.: Reconfigurable hardware—a case study in codesign. In: FPL: From FPGAs to Computing Paradigm. Lecture Notes in Computer Science, vol. 1482, pp. 451–455. Springer, Berlin (1998)Google Scholar
  26. 26.
    IEEE Std1076-1993. Standard VHDL Langage Reference Manual. IEEE (1993)Google Scholar
  27. 27.
    Moy, M.: Techniques and Tools for the verification of Systems-on-a-Chip at the Transaction Level. PhD thesis, Institut National Polytechnique de Grenoble, December 2005Google Scholar
  28. 28.
    Moy, M., Maraninchi, F., Maillet-Contoz, L.: LusSy: A toolbox for the analysis of systems-on-a-chip at the transactional level. In: International Conference on Application of Concurrency to System Design, Juin 2005Google Scholar
  29. 29.
    Moy, M., Maraninchi, F., Maillet-Contoz, L.: Pinapa: An extraction tool for SystemC descriptions of systems-on-a-chip. In: ACM International Conference on Embedded Software (EMSOFT’05), Jersey city, September 2005Google Scholar
  30. 30.
    Mueller, W., Dömer, R., Gerstlauer, A.: The formal execution semantics of SpecC. In: ISSS ’02: Proceedings of the 15th international symposium on System Synthesis, pp. 150–155. ACM Press, New York (2002)Google Scholar
  31. 31.
    Open SystemC Initiative. SystemC 2.0.1 Language Reference Manual (2004)Google Scholar
  32. 32.
    Pasricha, S.: Transaction level modeling of SoC in SystemC 2.0. Technical report, STMicroelectronics Ltd (2002)Google Scholar
  33. 33.
    Plosila, J., Sere, K.: Action systems in pipelined processor design. In: Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC ’97), pp. 156–166. IEEE Computer Society, Eindhoven, The Netherlands, 7–10 April 1997Google Scholar
  34. 34.
    Ruf J.: RAVEN: Real-time analyzing and verification environment. J. Univ. Comput. Sci. 7(1), 89–104 (2001)MATHGoogle Scholar
  35. 35.
    Ruf, J., Hoffmann, D., Gerlach, J., Kropf, T., Rosenstiehl, W., Mueller, W.: The simulation semantics of SystemC. In: DATE ’01: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 64–70. IEEE Press, Piscataway (2001)Google Scholar
  36. 36.
    Ruf, J., Hoffmann, D., Kropf, T., Rosenstiel, W.: Simulation-guided property checking based on a multi-valued AR-automata. In: DATE ’01: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 742–748. IEEE Press, Piscataway (2001)Google Scholar
  37. 37.
    Salem, A.: Formal semantics of synchronous SystemC. In DATE ’03: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 376–381. IEEE Computer Society, Washington (2003)Google Scholar
  38. 38.
    SOCFV Project. System on chip formal verification home page. (2004)
  39. 39.
    Synopsys Inc. Describing synthesizable RTL in SystemC. Technical report, Synopsys, November 2002Google Scholar
  40. 40.
    Talpin, J.-P., Le Guernic, P., Shukla, S.K., Gupta, R.K., Doucet, F.: Polychrony for formal refinement-checking in a system-level design methodology. In: 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), pp. 9–19. IEEE Computer Society, Guimaraes, 18–20 June 2003Google Scholar

Copyright information

© Springer-Verlag 2009

Authors and Affiliations

  • Dominique Cansell
    • 1
  • Dominique Méry
    • 2
  • Cyril Proch
    • 2
  1. 1.Université de Metz, LORIA CNRS UMR 7503Metz CédexFrance
  2. 2.Université Henri Poincaré Nancy 1, LORIA CNRS UMR 7503Vandœuvre-lès-NancyFrance

Personalised recommendations