Putting it all together – Formal verification of the VAMP

  • Sven Beyer
  • Christian Jacobi
  • Daniel Kröning
  • Dirk Leinenbach
  • Wolfgang J. Paul
Special section on Recent Advances in Hardware Verification

Abstract

In the verified architecture microprocessor (VAMP) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification has been carried out in the theorem proving system PVS. The processor has been implemented on a Xilinx FPGA.

Keywords

Formal methods Complete microprocessor verification Floating point unit Tomasulo scheduler Cache memory interface Theorem proving Model checking 

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Copyright information

© Springer-Verlag 2006

Authors and Affiliations

  • Sven Beyer
    • 1
  • Christian Jacobi
    • 3
  • Daniel Kröning
    • 4
  • Dirk Leinenbach
    • 2
  • Wolfgang J. Paul
    • 2
  1. 1.OneSpin Solutions GmbHMunichGermany
  2. 2.Computer Science DepartmentSaarland UniversitySaarbrückenGermany
  3. 3.IBM Deutschland Entwicklung GmbHBöblingenGermany
  4. 4.ETH Zürich, Computer Systems InstituteZürichSwitzerland

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