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Improved verification of hardware designs through antecedent conditioned slicing

  • Shobha VasudevanEmail author
  • E. Allen Emerson
  • Jacob A. Abraham
Special Section on Advances in Automated Verification of Critical Systems

Abstract

Static slicing has shown itself to be a valuable tool, facilitating the verification of hardware designs. In this paper, we present a sharpened notion, antecedent conditioned slicing that provides a more effective abstraction for reducing the size of the state space. In antecedent conditioned slicing, extra information from the antecedent is used to permit greater pruning of the state space. In a previous version of this paper, we applied antecedent conditioned slicing to safety properties of the form G(antecedentconsequent) where antecedent and consequent were written in propositional logic. In this paper, we use antecedent conditioned slicing to handle safety and bounded liveness property specifications written in linear time temporal logic. We present a theoretical justification of our technique. We provide experimental results on a Verilog RTL implementation of the USB 2.0 functional core, which is a large design with about 1,100 state elements (10331 states). The results demonstrate that the technique provides significant performance benefits over static program slicing using state-of-the-art model checkers.

Keywords

Hardware verification Model checking Program slicing LTL property Antecedent conditioned slicing Hardware description languages Verilog RTL 

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Copyright information

© Springer-Verlag 2006

Authors and Affiliations

  • Shobha Vasudevan
    • 1
    Email author
  • E. Allen Emerson
    • 2
  • Jacob A. Abraham
    • 1
  1. 1.Computer Engineering Research CenterUniversity of Texas at AustinAustinUSA
  2. 2.Department of Computer SciencesUniversity of Texas at AustinAustinUSA

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