Coverage metrics for formal verification

Special section on Recent Advances in Hardware Verification

DOI: 10.1007/s10009-004-0175-4

Cite this article as:
Chockler, H., Kupferman, O. & Vardi, M. Int J Softw Tools Technol Transfer (2006) 8: 373. doi:10.1007/s10009-004-0175-4


In formal verification, we verify that a system is correct with respect to a specification. Even when the system is proven to be correct, there is still a question of how complete the specification is and whether it really covers all the behaviors of the system. The challenge of making the verification process as exhaustive as possible is even more crucial in simulation-based verification, where the infeasible task of checking all input sequences is replaced by checking a test suite consisting of a finite subset of them. It is very important to measure the exhaustiveness of the test suite, and indeed there has been extensive research in the simulation-based verification community on coverage metrics, which provide such a measure. It turns out that no single measure can be absolute, leading to the development of numerous coverage metrics whose usage is determined by industrial verification methodologies. On the other hand, prior research of coverage in formal verification has focused solely on state-based coverage. In this paper we adapt the work done on coverage in simulation-based verification to the formal-verification setting in order to obtain new coverage metrics. Thus, for each of the metrics used in simulation-based verification, we present a corresponding metric that is suitable for the setting of formal verification and describe an algorithmic way to check it.


Formal verification Model checking Coverage metrics Algorithms 


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Copyright information

© Springer-Verlag 2006

Authors and Affiliations

  1. 1.IBM Research LabsMount CarmelHaifaIsrael
  2. 2.School of Engineering and Computer ScienceHebrew UniversityJerusalemIsrael
  3. 3.Department of Computer ScienceRice UniversityHoustonUSA

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