Design of memristor based low power and highly reliable ReRAM cell

  • Soumitra Pal
  • Subhankar Bose
  • Aminul IslamEmail author
Technical :Paper


A CNFET-based nonvolatile 4CNFET2M resistive RAM (ReRAM) cell is proposed in this paper. In this design, four CNFETs are employed as high-speed, low power and high endurance switches while the two memristors constitute the memory element. In this paper, the proposed 4CNFET2M ReRAM has been compared with the standard 6T SRAM (S6T) cell and the contemporary 2T2M ReRAM cell. The proposed cell shows 1.68 ×/2.14 × shorter read delay (TRA) when compared to S6T/2T2M while exhibiting 4.16 × shorter write delay (TWA) than that of 2T2M @ VDD = 1 V. Moreover, at VDD = 1 V, it displays a 2.32 × narrower spread in TWA than 2T2M as well as 8.0 ×/7.25 × narrower spread in TRA than that of S6T/2T2M. The proposed cell consumes 2.57 × 106 ×/2.70 × lower hold power (HPWR) than that of S6T/2T2M at VDD = 1 V. In addition, it exhibits tolerance to variations in temperature as well as pitch and Vth of memristor. All this is achieved at a 32.44 × penalty in TWA when compared to S6T. The use of CNFET devices, which possess far superior electrical characteristics in comparison to traditional CMOS devices, integrated with memristor technology, paves the way for such major improvements in design metrics of the proposed cell.



  1. Agarwal A, Mukhopadhyay S, Raychowdhury A, Roy K, Kim CH (2006) Leakage power analysis and reduction for nanoscale circuits. IEEE Micro 26(2):68–80CrossRefGoogle Scholar
  2. Ahmad S, Alam N, Hasan M (2018) Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications. AEU Int J Electron Commun 83:366–375CrossRefGoogle Scholar
  3. Ahmad S, Gupta MK, Alam N, Hasan M (2017) Low leakage single bitline 9 T (SB9T) static random access memory. Microelectronics J 62:1–11CrossRefGoogle Scholar
  4. Ali M, Ahmed M, Chrzanowska-jeske M (2015) Logical Effort model for CNFET—based circuits. In: IEEE International Conference on Nanotechnology, pp 1218–1221Google Scholar
  5. Alibart F, Gao L, Hoskins BD, Strukov DB (2012) High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm. Nanotechnology 23:7CrossRefGoogle Scholar
  6. Appenzeller J (2008) Carbon nanotubes for high-performance electronics—progress and prospect. Proc IEEE 96(2):201–211CrossRefGoogle Scholar
  7. Ashraf R, Nain RK, Chrzanowska-Jeske M, Narendra SG (2010) Design methodology for carbon nanotube based circuits in the presence of metallic tubes. In: Proc. 2010 IEEE/ACM Int. Symp. Nanoscale Archit. NANOARCH 2010, pp 71–76Google Scholar
  8. Batool SS et al (2013) Comparative analysis of Ti, Ni, and Au electrodes on characteristics of TiO2 nanofibers for humidity sensor application. J Mater Sci Technol 29(5):411–414MathSciNetCrossRefGoogle Scholar
  9. Biolek D, Di Ventra M, Pershin YV (2013) Reliable SPICE simulations of memristors, memcapacitors and meminductors. Radioengineering 22(4):945–968Google Scholar
  10. Buscarino A, Fortuna L, Frasca M, Valentina Gambuzza L (2012) A chaotic circuit based on Hewlett-Packard memristor. Chaos Interdiscip J Nonlinear Sci 22(2):023136MathSciNetCrossRefzbMATHGoogle Scholar
  11. Chain K, Huang JH, Duster J, Ko PK, Hu C (1997) A MOSFET electron mobility model of wide temperature range (77–400 K) for IC simulation. Semicond Sci Technol 12(4):355–358CrossRefGoogle Scholar
  12. Chiu PF et al (2012) Low store energy, low VDDmin, 8T2R nonvolatile latch and SRAM with vertical-stacked resistive memory (memristor) devices for low power mobile applications. IEEE J Solid-State Circ 47(6):1483–1496CrossRefGoogle Scholar
  13. Choi S, Sheridan P, Lu WD (2015) Data clustering using memristor networks. Sci Rep 5(1):10492CrossRefGoogle Scholar
  14. Chua LO (1971) Memristor—the missing circuit element. IEEE Trans Circ Theory 18(5):507–519CrossRefGoogle Scholar
  15. Deng J, Wong HSP (2007) A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part II: full device model and circuit performance benchmarking. IEEE Trans Electron Devices 54(12):3195–3205CrossRefGoogle Scholar
  16. Durant SM (2011) Building sustainable national monitoring networks. Biodivers Monit Conserv Bridg Gap Between Glob Commit Local Action 34(4):313–334Google Scholar
  17. Dwivedi P, Kumar K, Islam A (2016) Comparative study of subthreshold leakage in CNFET and MOSFET@32-nm technology node. Int Conf Microelectron Comput Commun MicroCom 2(1):2016Google Scholar
  18. Filanovsky IM, Allam A (2001) Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits. IEEE Trans Circ Syst I Fund Theory Appl 48(7):876–884CrossRefGoogle Scholar
  19. Garcia-Redondo F, Lopez-Vallejo M (2017) On the design and analysis of reliable RRAM-CMOS hybrid circuits. IEEE Trans Nanotechnol 16(3):514–522CrossRefGoogle Scholar
  20. Halawani Y, Mohammad B, Homouz D, Al-Qutayri M, Saleh H (2016) Modeling and optimization of memristor and STT-RAM-based memory for low-power applications. IEEE Trans Very Large Scale Integr Syst 24(3):1003–1014CrossRefGoogle Scholar
  21. Hashempour H, Lombardi F (2008) Device model for ballistic CNFETs using the first conducting band. IEEE Des Test Comput 25(2):178–186CrossRefGoogle Scholar
  22. Hu J, Stecklein G, Anugrah Y, Crowell PA, Koester SJ (2017) Using programmable graphene channels as weights in spin-diffusive neuromorphic computing. IEEE J Explor Solid-State Comput Dev Circ 4(1):26–34Google Scholar
  23. Huang GM, Ho Y (2014) Memristors for non-volatile memory and other applications. Adv Non-Volatile Mem Storage Technol 2014:370–397CrossRefGoogle Scholar
  24. Imran A, Hasan M, Islam A, Abbasi SA (2012) Optimized design of a 32-nm CNFET-based low-power ultrawideband CCII. IEEE Trans Nanotechnol 11(6):1100–1109CrossRefGoogle Scholar
  25. Islam A, Akram MW, Pable SD, Hasan M (2010) Statistical data stability and leakage evaluation of SRAM cell in sub-45 nm technology. In: IEEE Int Conf Adv Commun Network Comput, pp 149–152Google Scholar
  26. Keshavarzi A, Raychowdhury A, Member S, Kurtin J, Roy K, De V (2006) Carbon nanotube field-effect transistors for high-performance digital circuits—transient. IEEE Trans Electron Devices 53(11):2718–2726CrossRefGoogle Scholar
  27. Kim K, Shin S, Kang SM (2011) Field programmable stateful logic array. IEEE Trans Comput Des Integr Circ Syst 30(12):1800–1813MathSciNetCrossRefGoogle Scholar
  28. Kwon DH et al (2010) Atomic structure of conducting nanofilaments in TiO2 resistive switching memory. Nat Nanotechnol 5(2):148–153CrossRefGoogle Scholar
  29. Lehtonen E, Poikonen JH, Laiho M (2012) Applications and limitations of memristive implication logic. In: 13th international workshop on cellular nanoscale networks and their applicationsGoogle Scholar
  30. Li D, Tang P (2013) A sensor specified method based on spectral transformation for masking cloud in landsat data. IEEE J Sel Top Appl Earth Obs Remote Sens 6(3):1619–1627CrossRefGoogle Scholar
  31. Li T et al (2016) A novel test method for metallic CNTs in CNFET-Based SRAMs. IEEE Trans Comput Des Integr Circ Syst 35(7):1192–1205CrossRefGoogle Scholar
  32. Lu W, Lieber CM (2007) Nanoelectronics from the bottom up. Nat Mater 6(11):841–850CrossRefGoogle Scholar
  33. McEuen PL, Fuhrer MS, Park H (2002) Single-walled carbon nanotube electronics. IEEE Trans Nanotechnol 1(11):78–85CrossRefGoogle Scholar
  34. Meijer GI (2008) Materials science: who wins the nonvolatile memory race? Science 319(5870):1625–1626CrossRefGoogle Scholar
  35. Mountain DJ, McLean MR, Krieger CD (2018) Memristor crossbar tiles in a flexible, general purpose neural processor. IEEE J Emerg Sel Top Circ Syst 8(1):137–145CrossRefGoogle Scholar
  36. Navi K, Jasemi M, Bagherzadeh N, Faghih Mirzaee (2015) Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic. IET Circ Devices Syst 9(5):343–352CrossRefGoogle Scholar
  37. Ni L, Liu Z, Yu H, Joshi RV (2017) “SM: an energy-efficient digital ReRAM-crossbar-based CNN with bitwise parallelism. IEEE J Explor Solid-State Comput Dev Circ 3(April):37–46Google Scholar
  38. NIMO PTM model (2018) [online]. Accessed May 2018
  39. Pal S, Islam A (2016a) Variation tolerant differential 8T SRAM cell for ultralow power applications. IEEE Trans Comput Des Integr Circ Syst 35(4):549–558CrossRefGoogle Scholar
  40. Pal S, Islam A (2016b) 9-T SRAM cell for reliable ultralow-power applications and solving multibit soft-error issue. IEEE Trans Device Mater Reliab 16(2):172–182CrossRefGoogle Scholar
  41. Pal S, Gupta V, Islam A (2018) Variation resilient low-power memristor-based synchronous flip-flops: design and analysis. Microsyst Technol. Google Scholar
  42. Patil N, Lin A, Zhang J, Wong HSP, Mitra S (2009) Digital VLSI logic technology using carbon nanotube FETs: frequently asked questions. In: 2009 46th ACM/IEEE Des. Autom. Conf., pp 304–309Google Scholar
  43. Pershin YV, Fontaine SL, DiVentra M (2009) Memristive model of amoeba learning. Phys Rev E Stat Nonlinear Soft Matter Phys 80(2):1–18CrossRefGoogle Scholar
  44. Pershin YV, Slipko VA, DiVentra M (2013) Complex dynamics and scale invariance of one-dimensional memristive networks. Phys Rev E Stat Nonlinear Soft Matter Phys 87(2):1–8CrossRefGoogle Scholar
  45. Pickett MD, Medeiros-Ribeiro G, Williams RS (2013) A scalable neuristor built with Mott memristors. Nat Mater 12(2):114–117CrossRefGoogle Scholar
  46. Rose GS, Rajendran J, Manem H, Karri R, Pino RE (2012) Leveraging memristive systems in the construction of digital logic circuits. Proc IEEE 100(6):2033–2049CrossRefGoogle Scholar
  47. Roy C, Islam A (2016) TG based 2T2M RRAM using memristor as memory element. Indian J Sci Technol 9(33):7–11CrossRefGoogle Scholar
  48. Sakib MN, Hassan R, Biswas SN, Das SR (2018) Memristor-based high-speed memory cell with stable successive read operation. IEEE Trans Comput Des Integr Circ Syst 37(5):1037–1049Google Scholar
  49. Shin S, Kim K, Kang SM (2011) Memristor applications for programmable analog ICs. IEEE Trans Nanotechnol 10(2):266–274CrossRefGoogle Scholar
  50. Sinha SK, Chaudhury S (2014) Advantage of CNTFET characteristics over MOSFET to reduce leakage power. In: Proc. IEEE Int. Caracas Conf. Devices, Circuits Syst. ICCDCS, pp 1–5Google Scholar
  51. Strukov DB, Snider GS, Stewart DR, Williams RS (2008) The missing memristor found. Nature 453(7191):80–83CrossRefGoogle Scholar
  52. Sun J, Shen Y, Yin Q, Xu C (2013) Compound synchronization of four memristor chaotic oscillator systems and secure communication. Chaos Interdiscip J Nonlinear Sci 23(1):013140MathSciNetCrossRefzbMATHGoogle Scholar
  53. The Stanford CNFET model (2018) [Online]. Accessed May 2018
  54. Wu TF et al (2018) Hyperdimensional computing exploiting carbon nanotube fets, resistive ram, and their monolithic 3D integration. IEEE J Solid-State Circ PP:1–14Google Scholar
  55. Wulf WA, McKee SA (1995) Hitting the memory wall. ACM SIGARCH Comput Archit News 23(1):20–24CrossRefGoogle Scholar
  56. Yakopcic C, Taha TM, Subramanyam G, Pino RE, Rogers S (2011) A memristor device model. IEEE Electron Device Lett 32(10):1436–1438CrossRefGoogle Scholar
  57. Zhao H, Li L, Peng H, Kurths J, Xiao J, Yang Y (2015) Anti-synchronization for stochastic memristor-based neural networks with non-modeled dynamics via adaptive control approach. Eur. Phys. J. B 88:5MathSciNetGoogle Scholar
  58. Zidan MA, Fahmy HAH, Hussain MM, Salama KN (2013) Memristor-based memory: the sneak paths problem and solutions. Microelectronics J 44(2):176–183CrossRefGoogle Scholar

Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Electronic and Computer EngineeringThe Hong Kong University of Science and TechnologyClear Water BayHong Kong
  2. 2.Department of Electronics and Communication EngineeringBirla Institute of TechnologyRanchiIndia

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