FPGA implementation of high performance digital down converter for software defined radio

  • Debarshi DattaEmail author
  • Partha Mitra
  • Himadri Sekhar Dutta
Technical Paper


Digital down converter (DDC) is one of the crucial components in digital radio receiver. The working function of DDC is to convert the frequency translation from Intermediate Frequency (IF) band to baseband signal. This paper briefs a hardware efficient DDC architecture which is made of COordinate Rotation Digital Computer (CORDIC) processor act as a digital oscillator followed by multi-stage Cascaded Integrator Comb (CIC) performs as a high rate decimation filter and then Multi-channel Systolic Finite Impulse Response (MSFIR) decimation filter allows perfect output. All of these components of the proposed DDC architecture have been designed in Xilinx ISE 14.7 simulator using optimization techniques and targeted to the Xilinx Kintex-7 Field Programmable Gate Array (FPGA) device. Implementation of DDC on FPGA provides high flexibility, moderate cost and customizability. The result analysis of the proposed DDC model is superior to the similar design with regard to area, operating speed and power consumption. The implemented DDC design is used to transform input bandwidth from about 70 MHz to 137 kHz, matching in Software Defined Radio (SDR) system requirements.



The authors would like to thank Brainware Group of Institutions and Kalyani Government Engineering College for providing the ISE design suite 14.7 and Xilinx FPGA device.


  1. Agarwal A, Boppana L, Kodali R (2014) A fractional sample rate conversion filters for a software radio receiver on FPGA. IEEE Xplore. Google Scholar
  2. Altera Corporation (2017) AN639: Inferring stratix V DSP blocks for FIR filtering applicationsGoogle Scholar
  3. Chandra A, Chattopadhyay S (2016) Design of hardware efficient FIR filter: a review of the state-of-the-art approaches. Eng Sci Technol Int J 19(1):212–226. CrossRefGoogle Scholar
  4. Das S, Maity R, Maity NP (2018) VLSI-based pipeline architecture for reversible image watermarking by difference expansion with high-level synthesis approach, circuit. Circuit Syst Signal Process 37(4):1575–1593CrossRefGoogle Scholar
  5. Datta D, Mitra P, Dutta HS (2019) Implementation of universal modulator using CORDIC architecture in FPGA. In: Mandal J, Mukhopadhyay S, Dutta P, Dasgupta K (eds) Computational intelligence, communications, and business analytics. CICBA 2018. Communications in computer and information science, vol 1030, chapter 34. Springer, Singapore, pp 434–441. Google Scholar
  6. Dhar AS, Lakshmi B (2010) CORDIC architectures: a survey. VLSI Des. MathSciNetGoogle Scholar
  7. Fei-yu L, Wei-ming Q, Yan-yu W, Tai-lian L, Jin F, Jian-chuan Z (2009) Efficient WCDMA digital down converter design using system generator. In: IEEE international conference on space science and communication, 2009, pp 89–92Google Scholar
  8. Ghani U, Wasim M, Khan US, Saleem MM, Hassan A, Rashid N, Tiwana M, Hamza A, Kashif A (2018) Efficient FIR filter implementations for multichannel BCIs using Xilinx system generator. BioMed Res Int. Google Scholar
  9. Hatai I, Chakrabarti I (2011) A new high-performance digital FM modulator and demodulator for software-defined radio and its FPGA implementation. Int J Reconfig Comput. Google Scholar
  10. Hogenauer EB (1981) An economical class of digital filters for decimation and interpolation. IEEE Trans Acoust Speech Signal Process 29(2):155–162CrossRefGoogle Scholar
  11. Jing Q, Li Y, Tong J (2019) Performance analysis of multi-rate signal processing digital filters on FPGA. EURASIP J Wirel Commun Netw. Google Scholar
  12. Liu C, Wang Y (2015) A 128-channel, 710 M samples/second, and less than 10 ps RMS resolution time-to-digital converter implemented in a Kintex-7 FPGA. IEEE Trans Nucl Sci. Google Scholar
  13. Liu X, Yan X, Wang Z, Deng Q (2017) Design and FPGA implementation of a reconfigurable digital down converter for wideband applications. IEEE Trans VLSI Syst 25(12):3548–3552CrossRefGoogle Scholar
  14. Loehning M, Hentschel T, Fettweis G (2000) Digital down conversion in software radio terminals. In: 10th European signal processing conference, vol. 3, 2000, FinlandGoogle Scholar
  15. Meher P, Chandrasekaran S, Amira A (2007) FPGA Realization of FIR filters by efficient and flexible systolization using distributed arithmetic. IEEE Trans Signal Process 56(7):3009–3017. MathSciNetCrossRefzbMATHGoogle Scholar
  16. Obradović V, Okiljević P, Kozić N, Ivković D (2016) Practical implementation of digital down conversion for wideband direction finder on FPGA. Sci Tech Rev 66(4):40–46CrossRefGoogle Scholar
  17. Park YS (2015) A low-cost FPGA implementation of multi-channel FIR filter with variable bandwidth. IEICE Electron Express. Google Scholar
  18. Park SY, Meher PK (2014) Efficient FPGA and ASIC realizations of a DA-based reconfigurable FIR digital filter. IEEE Trans Circuits Syst II 61(7):511–515CrossRefGoogle Scholar
  19. Volder JE (1959) The CORDIC trigonometric computing technique. IRE Trans Electron Comput 8:330–334CrossRefGoogle Scholar
  20. Wolf W (2004) FPGA-based system design. Prentice-Hall, Englewood CliffsGoogle Scholar
  21. Zhang Q, Su X (2012) The design of digital down converter based on FPGA. In: 8th Internatinal conference on wireless communications, networking and mobile computing, IEEE Xplore, Shanghai, China.
  22. Zhang C, Zhang L (2016) Intermediate frequency digital receiver based on multi-FPGA system. J Electr Comput Eng. Google Scholar

Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  • Debarshi Datta
    • 1
    Email author
  • Partha Mitra
    • 1
  • Himadri Sekhar Dutta
    • 2
  1. 1.Department of Electronics and Communication EngineeringBrainware Group of InstitutionsKolkataIndia
  2. 2.Department of Electronics and Communication EngineeringKalyani Government Engineering CollegeNadiaIndia

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