Dual metal Schottky barrier asymmetric gate stack cylindrical gate all around (DM-SB-ASMGS-CGAA) MOSFET for improved analog performance for high frequency application

  • Shreya NandyEmail author
  • Sanjana Srivastava
  • Sonam Rewari
  • Vandana Nath
  • R. S. Gupta
Technical Paper


In this paper dual metal Schottky barrier asymmetric gate stack cylindrical gate all around (DM-SB-ASMGS-CGAA) MOSFET is analyzed for improvement in analog performance for applications with high frequency, using ATLAS 3D device simulator. This device is compared with conventional Schottky barrier MOSFET (SB-CGAA), Schottky barrier graded stack MOSFET (SBGS-CGAA) and dual metal graded channel stack Schottky barrier MOSFET (DMSBGS-CGAA) to analyze its analog performance and applications. It is observed that DM-SB-ASMGS MOSFET shows better performance in terms of high drain current, high transconductance, gain obtained from current (CG) and gain obtained from maximum transducer power (MTPG). Early voltage and intrinsic gain are desirable for the proposed device compared to the other devices showing its capability for high-gain amplification applications. The potential and electric field results are better for the proposed device compared to the previous device architectures. The subthreshold slope obtained for DM-SB-ASMGS MOSFET is 67 (mV/decade) which is lowest among the other comparable devices and so it is highly desirable for high frequency applications. Small signal AC analysis is also carried out in order to affirm with the analog performance results. The scattering parameters (S-parameters) are taken in account and shows that it gives better performance compared to its counterparts. The reflection coefficients that are S11, S22 show better matching to ports or minimum reflection. Also the parameters S12, S21 show higher voltage gains implying that the device can be used for high gains.



Authors are grateful to the Director Maharaja Agrasen Institute of Technology, Delhi for providing necessary facilities to carry out this research work.


  1. Arunprathap S, Napolean A, Azariah C (2014) Fabrication of thin film transistor using high K dielectric materials. Int J Eng Comput Sci 3(3):5387–5391Google Scholar
  2. ATLAS (2015) 3D Device Simulator, SILVACO InternationalGoogle Scholar
  3. Contreras E, Cerdeira A, Alvarado J, Pavanello M (2010) Application of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors. J Integr Circ Syst 5(2):110–115Google Scholar
  4. Fahad HM, Hussain MM (2013) High-performance silicon nanotubetunneling FET for ultralow-power logic applications. IEEE Trans Electron Devices 60(3):1034–1038CrossRefGoogle Scholar
  5. Gautam R, Saxena M, Gupta RS, Gupta M (2011) Impact of interface fixed charges on the performance of the channel material engineered cylindrical nanowire MOSFET. Int J VLSI Des Commun Syst (VLSICS) 2(3):225–241CrossRefGoogle Scholar
  6. Hamid HAE, Iñíguez B, Guitart J (2007) Analytical model of the threshold voltage and subthreshold swing of undoped cylindrical gate-all-around-based MOSFETs. IEEE Trans Electron Devices 54(3):72–579CrossRefGoogle Scholar
  7. Kang SM, Leblebici Y (2003) CMOS digital integrated circuits. Tata McGraw-Hill Education, New YorkGoogle Scholar
  8. Kaur H, Kabra S, Haldar S, Gupta R (2008) An analytical threshold voltage model for graded channel asymmetric gate stack (GCASYMGAS) surrounding gate MOSFET. Solid-State Electron 52(2):305–311CrossRefGoogle Scholar
  9. Kumar P, Bhowmick B (2017) 2D analytical model for surface potential based electric field and impact of wok function in DMG SB MOSFET. Superlattices Microstruct 109:805–814CrossRefGoogle Scholar
  10. Kumar M, Haldar S, Gupta M, Gupta RS (2014) Impact of gate material engineering (GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation. Microelectron J 45(11):1508–1514CrossRefGoogle Scholar
  11. Kumar M, Haldar S, Gupta M, Gupta R (2016a) Physics based analytical model for surface potential and subthreshold current of cylindrical Schottky Barrier gate all around MOSFET with high-k gate stack. Superlattices Microstruct 90:215–226CrossRefGoogle Scholar
  12. Kumar M, Haldar S, Gupta M, Gupta R (2016b) Analytical model of threshold voltage degradation due to localized charges in gate material engineered schottky barrier cylindrical GAA MOSFETs. Semicond Sci Technol 31(10):105013CrossRefGoogle Scholar
  13. Martin MJ, Pascual E, Rengel R (2012) RF dynamic and noise performance of Metallic Source/Drain SOI n-MOSFETs. Solid-State Electron 73:64–73CrossRefGoogle Scholar
  14. Narang M, Saxena RS, Gupta M (2011) Gupta, Linearity and analog performance analysis of double gate tunnel FET: effect of temperature and gate stack. Int J VLSI Des Commun Syst (VLSICS) 2(3):185–200CrossRefGoogle Scholar
  15. Rewari S, Haldar S, Nath V, Deswal S, Gupta R (2016a) Numerical modeling of subthreshold region of junctionless double surrounding gate MOSFET (JLDSG). Superlattices Microstruct 90:8–19CrossRefGoogle Scholar
  16. Rewari S, Nath V, Haldar S, Deswal SS, Gupta RS (2016b) Improved analog and AC performance with increased noise immunity using nanotube junctionless field effect transistor (NJLFET). Appl Phys A 122(12):1049CrossRefGoogle Scholar
  17. Rewari S, Nath V, Haldar S, Deswal S, Gupta R (2017) Hafnium oxide based cylindrical junctionless double surrounding gate (CJLDSG) MOSFET for high speed, high frequency digital and analog applications. Microsyst Technol. Google Scholar
  18. Shih C, Yeh S (2008) Device considerations and design optimizations for dopant segregated Schottky barrier MOSFETs. Semicond Sci Technol 23(12):125033CrossRefGoogle Scholar
  19. Tripathi S, Mishra R, Mishra R (2012) Multi-gate MOSFET structures with high-k dielectric materials. J Electron Devices 16:1388–1394Google Scholar
  20. Young K (1989) Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans Electron Devices 36(2):399–402CrossRefGoogle Scholar
  21. Zaunert F, Endres R, Stefanov Y, Schwalke U (2007) Evaluation of MOSFETs with crystalline high-k gate-dielectrics: device simulation and experimental data. J Telecommun Inf Technol 78–85Google Scholar
  22. Zhu G, Zhou X, Chin YK, Pey KL, Zhang J, See GH, Lin S, Yan Y (2010) Chen, Z, Subcircuit compact model for dopant-segregated Schottky gate-all-around Si-nanowire MOSFETs. IEEE Trans Electron Devices 57(4):772–781CrossRefGoogle Scholar

Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  • Shreya Nandy
    • 1
    Email author
  • Sanjana Srivastava
    • 1
  • Sonam Rewari
    • 1
  • Vandana Nath
    • 2
  • R. S. Gupta
    • 1
  1. 1.Department of Electronics and Communication EngineeringMaharaja Agrasen Institute of TechnologyNew DelhiIndia
  2. 2.University School of Information and Communication TechnologyGuru Gobind Singh Indraprastha UniversityNew DelhiIndia

Personalised recommendations