A fully CMOS RF down-converter with 81.88 dB SFDR for IEEE 802.15.4 based wireless systems

  • S. Chrisben GladsonEmail author
  • K. Alekhya
  • M. Bhaskar
Technical Paper


In this paper, the challenges of dense integration, low power, low-cost, low-noise and high spurious free dynamic range (SFDR) required by the RF front-end (RFE) circuits for low-rate wireless personal area networks are addressed. The proposed RF down-converter circuit utilizes a low-noise transconductance amplifier stage to improve the noise performance of the highly noisy switching stage of the down-converter. The nonlinearity of the low-noise stage is compensated by employing post-distortion based harmonic cancellation for dynamic range improvement of the RF front-end circuit. The proposed RFE is designed and realised in UMC 180 nm CMOS process technology. The post-layout characterization of the circuit shows an third-order intercept point with reference to the input (IIP3) of 11.83 dBm, double-sideband noise figure of 5.9 dB, conversion gain of 17.87 dB and offers a SFDR of 81.88 dB while consuming 5 mA current from 1.8 V. The proposed circuit consumes an area of 0.1 mm2. The proposed RF down-converter boasts a 17 dB improvement in SFDR over the recently proposed RFE in the literature. The proposed RFE is also correlated with the other existing state-of-art RFE circuits recorded in the literature for Zigbee applications.



This design project is supported by the Visvesvaraya Ph.D. scheme backed by the Ministry of Electronics and Information Technology (MeiTy), Govt. of India with Grant no. VISPHD-MEITY-1708.


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Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  1. 1.RF CMOS IC Design Lab, Department of Electronics and Communication EngineeringNational Institute of TechnologyTiruchirappalliIndia
  2. 2.Synopsys India, Private LimitedBangaloreIndia

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