Microsystem Technologies

, Volume 25, Issue 5, pp 1987–2009 | Cite as

Toffoli Netlist and QCA implementations for existing four variable reversible gates: a comparative analysis

  • Mahamuda Sultana
  • Ayan Chaudhuri
  • Diganta SenguptaEmail author
  • Atal Chaudhuri
Technical Paper


With CMOS reaching its fundamental physical heat threshold limits, reversible logic has emerged as a viable alternative due to its heat arresting attributes. CMOS started witnessing frequency issues with maximum clocking achieved in GHz. Quantum-Dot Cellular Automata (QCA) has already promised THz clocking speeds although in the nascent form. These two domains have set the stage for information lossless substitution of CMOS in near future. QCA implementation provides a realizable implementation of the theoretical reversibility concept. Till date several four variable application specific reversible gates have been proposed but they lack relevant quantum mapping using QCA. This paper proposes both the implementations—Toffoli Netlist designs for the gates using positive control lines (optimized designs using negative control lines wherever possible) and implementations using Quantum-Dot Cellular Automata. The relevant quantum metrics have also been provided for the respective implementations. We also provide the complexity analysis of the four variable reversible gates based on Hamming Distance. This paper is intended to serve as a benchmark for optimized gate choice from among the existing four variable reversible gates for complex Boolean realizations.



  1. Abedi D, Jaberipur G, Sangsefidi M (2015) Coplanar full adder in quantum-dot cellular automata via clock-zone-based crossover. IEEE Trans Nanotechnol 14(3):497–504CrossRefGoogle Scholar
  2. Arabzadeh M and Saeedi M (2013) (2008-2013, version 2.5) RCViewer + : a viewer/analyzer for reversible and quantum circuits. Accessed 29 July 2018
  3. Arun M, Saravanan S (2013) Reversible arithmetic logic gate (ALG) for quantum computation. Int J Intell Eng Syst 6(3):1–9Google Scholar
  4. Banerjee A (2010) PhD Thesis. [Online]. Accessed 29 July 2018
  5. Bennett CH (1973) Logical reversibility of computation. IBM J Res Dev 17(6):525–532MathSciNetzbMATHCrossRefGoogle Scholar
  6. Bérut A et al (2012) Experimental verification of Landauer’s principle linking information and thermodynamics. Nature 483(7388):187–189CrossRefGoogle Scholar
  7. Bhagyalakshmi HR, Venkatesha MK (2011) Design of a multifunction BVMF reversible logic gate and its applications. Int Journal Comput Appl 32(3):0975–8887Google Scholar
  8. Biswas AK, Hasan MM, Chowdhury AR, Babu HMH (2008) Efficient approaches for designing reversible binary coded decimal adders. Microelectron J Elsevier 39(12):1693–1703CrossRefGoogle Scholar
  9. Biswas P, Gupta N, Patidar N (2014) Basic reversible logic gates and it’s QCA implementation. Int J Eng Res Appl 4(6):12–16Google Scholar
  10. Campos CAT, Marciano AL, Neto OPV, Torres FS (2016) USE: a universal, scalable and efficient clocking scheme for QCA. IEEE Trans Comput Aided Des Integr Circuits Syst 35(3):513–517CrossRefGoogle Scholar
  11. Cho H, Swartzlander EE Jr (2007) Adder designs and analyses for quantum-dot cellular automata. IEEE Trans Nanotechnol 6(3):374–383CrossRefGoogle Scholar
  12. Cho H, Swartzlander EE (2009) Adder and multiplier design in quantum-dot cellular automata. IEEE Trans Comput 58(6):721–727MathSciNetzbMATHCrossRefGoogle Scholar
  13. Compaño R, Molenkamp L, Paul DJ (1999) Technology roadmap for nanoelectronics. In: European Commission IST programme Future and Emerging Technologies, 1999Google Scholar
  14. Datta K et al (2013) Exploiting negative control lines in the optimization of reversible circuits. In: International Conference on Reversible Computing, pp 209–220Google Scholar
  15. Datta K, Sengupta I, Rahaman H (2015) A post-synthesis optimization technique for reversible circuits exploiting negative control lines. IEEE Trans Comput 64(4):1208–1214MathSciNetzbMATHCrossRefGoogle Scholar
  16. Feynman RP (1982) Simulating physics with computers. Int J Theor Phys 21(6):467–488MathSciNetCrossRefGoogle Scholar
  17. Frank MP (2005) Introduction to reversible computing: motivation, progress and challenges. In: 2nd Conference on Computing Frontiers, 2005, pp 385–390Google Scholar
  18. Fredkin E, Toffoli T (1982) Conservative logic. Int J Theor Phys 21:219–253MathSciNetzbMATHCrossRefGoogle Scholar
  19. Gladshtein M (2011) Quantum-dot cellular automata serial decimal adder. IEEE Trans Nanotechnol 10(6):1377–1382CrossRefGoogle Scholar
  20. Haghparast M, Navi K (2007) A novel reversible full adder circuit for nanotechnology based systems. J Appl Sci 7(24):3995–4000CrossRefGoogle Scholar
  21. Haghparast M, Navi K (2008) A novel reversible BCD adder for nanotechnology based systems. Am J Appl Sci 5(3):282–288CrossRefGoogle Scholar
  22. Islam MS, Rahman MM, Begum Z (2009) Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders. In: International Conference on Advances in Computational Tools for Engineering Applications, 2009. ACTEA ‘09, 2009, pp 396-401Google Scholar
  23. James RK, Jacob KP, Sasi S (2012) Design of compact reversible decimal adder using RPS gates. In: World Congress on Information and Communication Technologies (WICT), 2012, pp 344–349Google Scholar
  24. Kim K, Wu K, Karri R (2007) The robust QCA adder designs using composable QCA building blocks. IEEE Trans Comput Aided Des Integr Circuits Syst 26(1):176–183CrossRefGoogle Scholar
  25. Landauer R (1961) Irreversibility and heat generation in the computing process. IBM J Res Dev 5(3):183–191MathSciNetzbMATHCrossRefGoogle Scholar
  26. Lent CS, Isaksen B (2003) Clocked molecular quantum-dot cellular automata. IEEE Trans Electron Devices 50(9):1890–1896CrossRefGoogle Scholar
  27. Lent CS, Tougaw PD, Porod W (1994) Quantum cellular automata: the physics of computing with arrays of quantum dot molecules. In: Workshop on Physics and Computation, 1994. PhysComp ‘94, 1994, pp 5–13Google Scholar
  28. Liu W, Liang L, O’Neill M, Swartzlander EE Jr, Woods R (2011) Design of quantum-dot cellular automata circuits using cut-set retiming. IEEE Trans Nanotechnol 10(5):1150–1160CrossRefGoogle Scholar
  29. Liu W, Liang L, O’Neill M, Swartzlander EE Jr (2014) A first step toward cost functions for quantum-dot cellular automata designs. IEEE Trans Nanotechnol 13(3):476–487CrossRefGoogle Scholar
  30. Maity GK, Maity SP (2012) Implementation of HNG using MZI. In: Third International Conference on Computing Communication and Networking Technologies (ICCCNT), 2012, pp 1–6Google Scholar
  31. Maslov D and Dueck GW (2006) Level compaction in quantum circuits In: IEEE Congress on Evolutionary Computing, pp 2405–2409Google Scholar
  32. Maslov D, Dueck GW, Miller DM (2005a) Synthesis of Fredkin-Toffoli reversible networks. IEEE Trans Very Large Scale Integr VLSI Syst 13(6):765–769CrossRefGoogle Scholar
  33. Maslov D, Dueck GW, Michael D (2005b) Toffoli network synthesis with templates. IEEE Trans Comput Aided Des Integr Circuits Syst 24(6):807–817CrossRefGoogle Scholar
  34. Miller DM, Maslov D, Dueck GW (2003) A transformation based algorithm for reversible logic synthesis. In: Design Automation Conference, pp 318–323Google Scholar
  35. Nielson M, Chuang I (2000) Quantum computation and quantum information. Cambridge University Press, CambridgeGoogle Scholar
  36. Niemier MT, Kogge PM (2001) Problems in designing with QCAs: Layout = Timing. Int J Circuit Theory Appl 29:49–62CrossRefGoogle Scholar
  37. Peres A (1985) Reversible logic and quantum computers. Phys Rev A 32(6):3266MathSciNetCrossRefGoogle Scholar
  38. Perri S, Corsonello P, Cocorullo G (2014) Area-delay efficient binary adders in QCA. IEEE Trans Very Large Scale Integr VLSI Syst 22(5):1174–1179CrossRefGoogle Scholar
  39. Porod W et al (1999) Quantum-dot cellular automata: computing with coupled quantum dots. Int J Electron 86(5):590–649CrossRefGoogle Scholar
  40. Pudi V, Sridharan K (2011) Efficient design of a hybrid adder in quantum-dot cellular automata. IEEE Trans Very Large Scale Integr VLSI Syst 19(9):1535–1548CrossRefGoogle Scholar
  41. Rashmi SB, Umarani TG, Shreedhar HK (2011) Optimized reversible montgomery multiplier. Int J Comput Sci Inf Technol 2(2):701–706Google Scholar
  42. Sengupta D, Sultana M, Chaudhuri A (2011) Realization of a novel reversible SCG gate and its application for designing parallel adder/subtractor and match logic. Int J Comput Appl 31(9):30–35Google Scholar
  43. Tahoori MB, Huang J, Momenzadeh M, Lombardi F (2004) Testing of quantum cellular automata. IEEE Trans Nanotechnol 3(4):432–442CrossRefGoogle Scholar
  44. Taskin B, Hong B (2008) Improving line based QCA memory cell design through dual phase clocking. IEEE Trans VLSI 16(12):1648–1656CrossRefGoogle Scholar
  45. Thapliyal H, Srinivas MB (2005) Novel reversible `TSG’ Gate and Its application for designing components of primitive reversible/quantum ALU. In: Fifth International Conference on Information, Communications and Signal Processing, 2005Google Scholar
  46. Toffoli T (1980) Reversible computing. MIT Lab for Computer Science, Tech Memo MIT/LCS/TM-151, 1980Google Scholar
  47. Vankamamidi V, Ottavi M, Lombardi F (2008) Two-dimensional schemes for clocking/timing of QCA circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 27(1):34–44zbMATHCrossRefGoogle Scholar
  48. Vasudevan DP, Lala PK, Di J, Parkerson JP (2006) Reversible-logic design with online testability. IEEE Trans Instr Meas 55(2):406–414CrossRefGoogle Scholar
  49. Walus K, Dysart TJ, Jullien GA (2004) QCADesigner: a rapid design and Simulation tool for quantum-dot cellular automata. IEEE Trans Nanotechnol 3(1):26–31CrossRefGoogle Scholar
  50. Wang R et al (2016) Effect of a clock system on bis-ferrocene molecular QCA. IEEE Trans Nanotechnol 15(4):574–582CrossRefGoogle Scholar
  51. Zhirnov VV, Cavin RK, Hutchby JA, Bourianoff GI (2003) Limits to binary logic switch scaling—a Gedaken model. Proc IEEE 91(11):1934–1939CrossRefGoogle Scholar

Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of CSETechno International New TownKolkataIndia
  2. 2.Department of ITTechno IndiaKolkataIndia
  3. 3.Department of CSETechno International BatanagarKolkataIndia
  4. 4.Department of CSEJadavpur UniversityKolkataIndia

Personalised recommendations