TSV constraints related to temperature excursion, pressure during molding, materials used and handling loads
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The current paper focuses on several mechanical aspects of a waferlevel packaging approach using a direct face-to-face Chip-to-Wafer (C2W) bonding of a MEMS device on an ASIC substrate wafer. Requirements of minimized inherent stress from packaging and good decoupling from forces applied in manufacturing and application are discussed with particular attention to the presence of through-silicon vias (TSV) in the substrate wafer. The paper deals with FEM analysis of temperature excursion, pressure during molding, materials used and handling load influence on mechanical stress within the TSV system and on wafer level, which can be large enough to disintegrate the system.
KeywordsPrincipal Stress Silicon Wafer AlCu High Hydrostatic Pressure Maximum Principal Stress
The authors would like to thank the European Community for the financial support of the presented work within the DAVID project (Sixth European Framework Programme, IST-027240).
- Coletti G et al (2005) Mechanical strength of silicon wafers and its modeling. In: Proceedings of 15th workshop on crystalline silicon solar cells and modules, Vail Colorado, USA, 7–10 August 2005Google Scholar
- Coletti G et al (2006) Mechanical strength of silicon wafers depending on wafer thickness and surface treatment. In: Proceedings of 21st European photovoltaic solar energy conference and exhibition, Dresden, Germany, 4–8 September 2006Google Scholar
- Pecht M et al (1999) Electronic packaging, materials and their properties. CRC Press, WashingtonGoogle Scholar
- Steinzig M (2000) Bend tests of silicon ladders to determine ultimate strength. HYTEC Incorporated report HTN-102050-0016, 08/03/2000Google Scholar