Microsystem Technologies

, Volume 15, Issue 1, pp 181–190 | Cite as

TSV constraints related to temperature excursion, pressure during molding, materials used and handling loads

  • Tomasz FałatEmail author
  • Kazimierz Friedel
  • Norman Marenco
  • Stephan Warnat
Technical Paper


The current paper focuses on several mechanical aspects of a waferlevel packaging approach using a direct face-to-face Chip-to-Wafer (C2W) bonding of a MEMS device on an ASIC substrate wafer. Requirements of minimized inherent stress from packaging and good decoupling from forces applied in manufacturing and application are discussed with particular attention to the presence of through-silicon vias (TSV) in the substrate wafer. The paper deals with FEM analysis of temperature excursion, pressure during molding, materials used and handling load influence on mechanical stress within the TSV system and on wafer level, which can be large enough to disintegrate the system.


Principal Stress Silicon Wafer AlCu High Hydrostatic Pressure Maximum Principal Stress 
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The authors would like to thank the European Community for the financial support of the presented work within the DAVID project (Sixth European Framework Programme, IST-027240).


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Copyright information

© Springer-Verlag 2008

Authors and Affiliations

  • Tomasz Fałat
    • 1
    Email author
  • Kazimierz Friedel
    • 1
  • Norman Marenco
    • 2
  • Stephan Warnat
    • 2
  1. 1.Faculty of Microsystem Electronics and FotonicsWrocław University of TechnologyWroclawPoland
  2. 2.Fraunhofer Institute for Silicon TechnologyItzehoeGermany

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