Advertisement

Neural Computing and Applications

, Volume 19, Issue 2, pp 283–297 | Cite as

Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices

  • Mohamed Boubaker
  • Mohamed Akil
  • Khaled Ben Khalifa
  • Thierry Grandpierre
  • Mohamed Hedi Bedoui
Original Article

Abstract

This paper presents an optimizing methodology for the implementation of a Learning Vector Quantization (LVQ) neural network in a Field Programmable Gate Array (FPGA) device. Starting from an algorithmic specification in the form of a Factorized and Conditioned Data Dependence Graph (GFCDD), we suggest a design methodology of the LVQ-dedicated architecture. This formal methodology is called AAA, “Algorithm Architecture Adequation”. Using graph transformations, it allows the generation of an optimized circuit implementation at the Register Transfer Level (RTL). It is associated to the SynDEx-IC software tool. Based on this formal methodology, we are able to explore and generate various LVQ network implementations by varying the LVQ sizes while minimizing the hardware resources and the design time. In addition, real-time constraints should be respected to ensure a reliable classification of vigilance states in humans from electroencephalographic signals (EEG). To validate our approach, the optimized LVQ implementation was tried on two types of Virtex devices.

Keywords

Variable size LVQ Co-design methodology Optimization Heuristics FPGA implementation Rapid prototyping 

References

  1. 1.
    Vuckovic A, Radivojevic V, Chen AC, Popovic D (2002) Automatic recognition of alertness and drowsiness from EEG by an artificial neural network. Med Eng Phys 24(5):349–360. doi: 10.1016/S1350-4533(02)00030-9 CrossRefGoogle Scholar
  2. 2.
    Ben Khalifa K, Bedoui MH, Dogui M, Alexandre F (2004) Analysis of vigilance states by neural networks. Proc ICTTA 2004, pp 429–430. doi: 10.1109/ICTTA.2004.1307815
  3. 3.
    Nakamoto T, Ozawa T, Shibata Y (2003) Improvement of odor recognition chip. Proc IEEE sensors, pp 1203–1208. doi: 10.1109/ICSENS.2003.1279136
  4. 4.
    Kugler M, Lopes M (2007) A configware approach for the implementation of a LVQ neural network. Int J Comput Intell Res 3(1):21–25Google Scholar
  5. 5.
    Ben Khalifa K, Girau B, Alexandre F, Bedoui MH (2004) Parallel FPGA implementation of self-organizing maps. Proc ICM 2004, pp 709–712. doi: 10.1109/ICM.2004.1434765
  6. 6.
    Curcio G, Casagrande M, Bertini M (2001) Sleepiness: evaluating and quantifying methods. Int J Psychophysiol 41(3):251–263. doi: 10.1016/S0167-8760(01)00138-6 CrossRefGoogle Scholar
  7. 7.
    Kerkeni N, Alexandre F, Bedoui MH, Bougrain L, Dogui M (2005) Neuronal spectral analysis of EEG and expert knowledge integration for automatic classification of sleep stages. In: WSEAS transactions on information science and applications 11(2):1854–1861Google Scholar
  8. 8.
    Grandpierre T, Sorel Y (2003) From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow graphs transformations. Proc MEMCODE 2003, pp 123–133. doi: 10.1109/MEMCOD.2003.1210097
  9. 9.
    Kaouane L, Akil M, Sorel Y, Grandpierre T (2004) A methodology to implement real-time applications onto reconfigurable devices. J Supercomput 30(3):283–301. doi: 10.1023/B:SUPE.0000045213.82276.8e CrossRefGoogle Scholar
  10. 10.
    Kohonen T (2001) Self-organizing maps. Springer, Berlin. ISBN: 3-540-67921-9, ISSN: 0720-678XGoogle Scholar

Copyright information

© Springer-Verlag London Limited 2009

Authors and Affiliations

  • Mohamed Boubaker
    • 1
  • Mohamed Akil
    • 2
  • Khaled Ben Khalifa
    • 1
  • Thierry Grandpierre
    • 2
  • Mohamed Hedi Bedoui
    • 1
  1. 1.Team TIM, Laboratory of BiophysicsFaculty of Medicine of MonastirMonastirTunisia
  2. 2.Laboratoire d’Informatique Gaspard-Monge, Equipe A3SI, ESIEE ParisUniversité Paris-EstNoisy Le Grand CedexFrance

Personalised recommendations