Neural Computing and Applications

, Volume 19, Issue 2, pp 283–297 | Cite as

Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices

  • Mohamed Boubaker
  • Mohamed Akil
  • Khaled Ben Khalifa
  • Thierry Grandpierre
  • Mohamed Hedi Bedoui
Original Article


This paper presents an optimizing methodology for the implementation of a Learning Vector Quantization (LVQ) neural network in a Field Programmable Gate Array (FPGA) device. Starting from an algorithmic specification in the form of a Factorized and Conditioned Data Dependence Graph (GFCDD), we suggest a design methodology of the LVQ-dedicated architecture. This formal methodology is called AAA, “Algorithm Architecture Adequation”. Using graph transformations, it allows the generation of an optimized circuit implementation at the Register Transfer Level (RTL). It is associated to the SynDEx-IC software tool. Based on this formal methodology, we are able to explore and generate various LVQ network implementations by varying the LVQ sizes while minimizing the hardware resources and the design time. In addition, real-time constraints should be respected to ensure a reliable classification of vigilance states in humans from electroencephalographic signals (EEG). To validate our approach, the optimized LVQ implementation was tried on two types of Virtex devices.


Variable size LVQ Co-design methodology Optimization Heuristics FPGA implementation Rapid prototyping 


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Copyright information

© Springer-Verlag London Limited 2009

Authors and Affiliations

  • Mohamed Boubaker
    • 1
  • Mohamed Akil
    • 2
  • Khaled Ben Khalifa
    • 1
  • Thierry Grandpierre
    • 2
  • Mohamed Hedi Bedoui
    • 1
  1. 1.Team TIM, Laboratory of BiophysicsFaculty of Medicine of MonastirMonastirTunisia
  2. 2.Laboratoire d’Informatique Gaspard-Monge, Equipe A3SI, ESIEE ParisUniversité Paris-EstNoisy Le Grand CedexFrance

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