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Soft Computing

, Volume 20, Issue 6, pp 2451–2465 | Cite as

Optimizing L1 cache for embedded systems through grammatical evolution

  • Josefa Díaz Álvarez
  • J. Manuel Colmenar
  • José L. Risco-Martín
  • Juan Lanchares
  • Oscar Garnica
Methodologies and Application

Abstract

Nowadays, embedded systems are provided with cache memories that are large enough to influence in both performance and energy consumption as never occurred before in this kind of systems. In addition, the cache memory system has been identified as a component that improves those metrics by adapting its configuration according to the memory access patterns of the applications being run. However, given that cache memories have many parameters which may be set to a high number of different values, designers are faced with a wide and time-consuming exploration space. In this paper, we propose an optimization framework based on Grammatical Evolution (GE) which is able to efficiently find the best cache configurations for a given set of benchmark applications. This metaheuristic allows an important reduction of the optimization runtime obtaining good results in a low number of generations. Besides, this reduction is also increased due to the efficient storage of evaluated caches. Moreover, we selected GE because the plasticity of the grammar eases the creation of phenotypes that form the call to the cache simulator required for the evaluation of the different configurations. Experimental results for the Mediabench suite show that our proposal is able to find cache configurations that obtain an average improvement of 62 % versus a real world baseline configuration.

Keywords

Execution Time Embed System Cache Size Data Cache Cache Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

Part of this research was supported by the Spanish Ministerio de economía y competitividad, project UEX: EPHEMECH: Algoritmos bioinspirados en entornos efímeros complejos. Id: IN2014-56494-C4-2-P.

References

  1. ARM Ltd (2013) ARM9 Processor Family. http://www.arm.com/products/processors/classic/arm9/
  2. ARM946E-S TM (2014) Technical reference manual. http://www.arm.com/products/processors/classic/arm9/arm946.php
  3. Brabazon A, O’Neill M (2006) Biologically inspired algorithms for financial modelling. Springer, New YorkzbMATHGoogle Scholar
  4. Burger D, Austin TM (1997) The simplescalar tool set, version 2.0. In: Technical Report, pp CS-TR-97-1342. University of Wisconsin-MadisonGoogle Scholar
  5. Byrne J, McDermott J, Galvaón-Loópez E, O’Neill M (2010) Implementing an intuitive mutation operator for interactive evolutionary 3d design. In: 2010 IEEE Congress on Evolutionary Computation (CEC), pp 1–7. doi: 10.1109/CEC.2010.5586485
  6. Chakrapani LN, Gyllenhaal J, Mei W, Hwu W, Mahlke SA, Palem KV, Rabbah RM (2005) Trimaran: An infrastructure for research in instruction-level parallelism. In: Instruction-level parallelism. Lecture notes in computer science. URL: http://www.trimaran.org/
  7. Chen L, Zou X, Lei J, Liu Z (2007) Dynamically reconfigurable cache for low-power embedded system. In: Third International Conference on Natural Computation, 2007, ICNC 2007, vol 5, pp 180–184. doi: 10.1109/ICNC.2007.346
  8. Dani A, Srikant Y, Amrutur B (2012) Efficient cache exploration method for a tiled chip multiprocessor. In: 2012 19th International Conference on High Performance Computing (HiPC), pp 1–6. doi: 10.1109/HiPC.2012.6507524
  9. Deb K, Pratap A, Agarwal S, Meyarivan T (2002) A fast and elitist multiobjective genetic algorithm: Nsga-ii. IEEE Trans Evol Comput 6(2):182–197. doi: 10.1109/4235.996017 CrossRefGoogle Scholar
  10. Dempsey I, O’Neill M, Brabazon A (2009) Foundations in Grammatical Evolution for Dynamic Environments, Studies in Computational Intelligence, vol 194. Springer. http://www.springer.com/engineering/book/978-3-642-00313-4
  11. Edler J, Hill MD (1998) Dinero iv trace-driven uniprocessor cache simulator. http://pages.cs.wisc.edu/markhill/DineroIV/
  12. Galván-López E, Swafford J, O’Neill M, Brabazon A (2010) Evolving a ms. pacman controller using grammatical evolution. In: Chio C, Cagnoni S, Cotta C, Ebner M, Ekrt A, Esparcia-Alcazar A, Goh CK, Merelo J, Neri F, Preu M, Togelius J, Yannakakis G (eds) Applications of Evolutionary Computation, Lecture Notes in Computer Science, vol 6024. Springer, Berlin Heidelberg, pp 161–170. doi: 10.1007/978-3-642-12239-2_17. http://dx.doi.org/10.1007/978-3-642-12239-2_17
  13. Gordon-Ross A, Lau J, Calder B (2008) Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy. In: Proceedings of the 18th ACM Great Lakes symposium on VLSI, GLSVLSI ’08. ACM, New York, NY, USA, pp 379–382. doi: 10.1145/1366110.1366200
  14. Hennessy JL, Patterson DA (2011) Computer architecture: a quantitative approach. Morgan KaufmannGoogle Scholar
  15. Janapsatya A, Ignjatovic A, Parameswaran S (2006) Finding optimal l1 cache configuration for embedded systems. In: Asia and South Pacific Conference on Design Automation, 2006, p 6. doi: 10.1109/ASPDAC.2006.1594783
  16. Koza JR, Poli R (2003) Introductory tutorials in optimization, search and decision supportGoogle Scholar
  17. Lee C, Potkonjak M, Mangione-Smith WH (1997) Mediabench: a tool for evaluating and synthesizing multimedia and communicatons systems. In: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, MICRO 30. IEEE Computer Society, Washington, DC, USA, pp 330–335. http://dl.acm.org/citation.cfm?id=266800.266832
  18. Mamidipaka M, Dutt N (2004) eCACTI: An enhanced power estimation model for on-chip caches. Tech. Rep. TR-04-28, CECS, UC IrvineGoogle Scholar
  19. Naz A, Kavi K, Rezaei M, Li W (2005) Making a case for split data caches for embedded applications. SIGARCH Comput Archit News 34(1):19–26. doi: 10.1145/1147349.1147355 CrossRefGoogle Scholar
  20. O’Neill M, Ryan C (2001) Grammatical evolution. IEEE Trans Evol Comput 5(4):349–358CrossRefGoogle Scholar
  21. O’Neill M, Ryan C (2003) Grammatical evolution: evolutionary automatic programming in an arbitrary language. Kluwer Academic Publishers, DordrechtCrossRefzbMATHGoogle Scholar
  22. O’Neill M, Hemberg E, Gilligan C, Bartley E, McDermott J, Brabazon A (2008) GEVA—grammatical evolution in Java. SIGEVOlution 3(2):17–22. doi: 10.1145/1527063.1527066 CrossRefGoogle Scholar
  23. O’Neill M, Ryan C (1999) Automatic generation of caching algorithms. In: Evolutionary Algorithms in Engineering and Computer Science. Wiley, pp 127–134Google Scholar
  24. Palesi M, Givargis T (2002) Multi-objective design space exploration using genetic algorithms. In: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002, CODES 2002, pp 67–72. doi: 10.1109/CODES.2002.1003603
  25. Perez D, Nicolau M, O’Neill M, Brabazon A (2011) Evolving behaviour trees for the mario ai competition using grammatical evolution. In: Chio C, Cagnoni S, Cotta C, Ebner M, Ekrt A, Esparcia-Alcázar A, Merelo J, Neri F, Preuss M, Richter H, Togelius J, Yannakakis G (eds) Applications of Evolutionary Computation, Lecture Notes in Computer Science, vol 6624. Springer, Berlin Heidelberg, pp 123–132. doi: 10.1007/978-3-642-20525-5_13
  26. Risco-Martín JL, Colmenar JM, Hidalgo JI, Lanchares J, Díaz J (2014) A methodology to automatically optimize dynamic memory managers applying grammatical evolution. J Syst Softw 91(0), 109–123 (2014). doi: 10.1016/j.jss.2013.12.044. http://www.sciencedirect.com/science/article/pii/S016412121400017X
  27. Risco-Martín JL, Colmenar JM (2013) Java Evolutionary COmputation library (JECO). Available at https://sourceforge.net/projects/jeco
  28. Shaker N, Nicolau M, Yannakakis G, Togelius J, O’Neill M (2012) Evolving levels for super mario bros using grammatical evolution. In: 2012 IEEE Conference on Computational Intelligence and Games (CIG), pp 304–311. doi: 10.1109/CIG.2012.6374170
  29. Silva-Filho A, Bastos-Filho C, Falcao D, Cordeiro F, Castro R (2008) An optimization mechanism intended for two-level cache hierarchy to improve energy and performance using the nsgaii algorithm. In: SBAC-PAD ’08. 20th International Symposium on Computer Architecture and High Performance Computing, 2008, pp 19–26. doi: 10.1109/SBAC-PAD.2008.9
  30. Varma A, Debes E, Kozintsev I, Jacob B (2005) Instruction-level power dissipation in the intel xscale embedded microprocessor. In: SPIEs 17th Annual Symposium on Electronic Imaging Science & TechnologyGoogle Scholar
  31. Wang W, Mishra P, Gordon-Ross A (2012) Dynamic cache reconfiguration for soft real-time systems. ACM Trans Embed Comput Syst 11(2):28:1–28:31. doi: 10.1145/2220336.2220340 CrossRefGoogle Scholar
  32. Wang W, Mishra P (2009) Dynamic reconfiguration of two-level caches in soft real-time embedded systems. In: IEEE Computer Society Annual Symposium on VLSI, 2009, ISVLSI ’09, pp 145–150. doi: 10.1109/ISVLSI.2009.22
  33. Wang W, Mishra P, Ranka S (2011) Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems. In: Proceedings of the 48th Design Automation Conference. ACM, New York, NY, USA, pp 948–953. doi: 10.1145/2024724.2024935

Copyright information

© Springer-Verlag Berlin Heidelberg 2015

Authors and Affiliations

  • Josefa Díaz Álvarez
    • 1
  • J. Manuel Colmenar
    • 2
  • José L. Risco-Martín
    • 3
  • Juan Lanchares
    • 3
  • Oscar Garnica
    • 3
  1. 1.Centro Universitario de MéridaUniversidad de ExtremaduraMéridaSpain
  2. 2.Department of Computer Science and StatisticsUniversidad Rey Juan CarlosMóstolesSpain
  3. 3.Department of Computer Architecture and AutomationUniversidad Complutense de MadridMadridSpain

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