Soft Computing

, Volume 11, Issue 9, pp 865–872 | Cite as

VLSI implementation of greedy-based distributed routing schemes for ad hoc networks

  • Alberto Aloisio
  • Vincenzo Izzo
  • Salvatore Rampone
Original Paper

Abstract

We describe a VLSI implementation based on a FPGA of a new greedy algorithm for approximating minimum set covering in ad hoc wireless network applications. The implementation makes the algorithm suitable for embedded and real-time architectures. The algorithm, while not randomized, is based on a probability distribution that leads the greedy choice. The algorithm has been specifically tailored to run on platforms with minimal computational hardware.

Keywords

Ad hoc wireless network Greedy algorithm Minimum set cover FPGA implementation 

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Copyright information

© Springer-Verlag 2006

Authors and Affiliations

  • Alberto Aloisio
    • 1
  • Vincenzo Izzo
    • 1
  • Salvatore Rampone
    • 2
  1. 1.Dipartimento di Scienze Fisiche and INFNUniversità di Napoli “Federico II”NapoliItaly
  2. 2.Research Centre on Software Technology (RCOST) and DSGAUniversità del SannioBeneventoItaly

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