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Device physics and design of hetero-gate dielectric tunnel field-effect transistors with different low/high-k EOT ratios


The hetero-gate dielectric (HGD) structure was recently experimentally demonstrated to enhance the electrical performance of tunnel field-effect transistors (TFETs). This study examined the mechanisms underlying the HGD structure functioning and investigated the design of the structure to enhance the electrical characteristics of TFETs with different ratios of low- and high-k equivalent oxide thicknesses (EOT). The on-current enhancement by the source-side dielectric heterojunction, which directly modulates the on-state tunnel width, was much larger than that by the drain-side dielectric heterojunction, which indirectly affects the on-current by modulating the subthreshold tunnel width. The subthreshold swing is improved by the formation of a conduction band well near the source-channel junction. However, the swing improvement is limited by the hump effect when this local potential well approaches the source. The optimal design of the HGD structure and the maximal enhancement of on-current considerably depend on the EOT ratio of low- and high-k dielectrics. The on-current is most enhanced by the optimized HGD structure at a low/high-k EOT ratio of ten times, that is, approximately 160% of the on-current of the uniform high-k TFET counterpart. Due to the continuous trend of increasing the k-values or scaling EOTs, understanding the dependence of device physics and design on the low/high-k EOT ratio is crucial to optimize the performance of HGD-TFETs.

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Change history

  • 21 January 2020

    The correct name of the third author should be given as Huu-Duy Tran, not Huy-Duy Tran.


  1. 1.

    IEEE International Roadmap for Devices and Systems (IRDS) (2018)

  2. 2.

    J. Appenzeller, Y.-M. Lin, J. Knoch, Ph Avouris, Band-to-band tunneling in carbon nanotube field-effect transistors. Phys. Rev. Lett. 93, 196905 (2004)

  3. 3.

    W.Y. Choi, B.-G. Park, J.D. Lee, T.-J.K. Liu, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28, 743–745 (2007)

  4. 4.

    S.O. Koswatta, M.S. Lundstrom, D.E. Nikonov, Performance comparison between p-i-n tunneling transistors and conventional MOSFETs. IEEE Trans. Electron Devices 56, 456–465 (2009)

  5. 5.

    M.G. Bardon, H.P. Neves, R. Puers, C.V. Hoof, Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions. IEEE Trans. Electron Devices 57, 827–834 (2010)

  6. 6.

    A.C. Seabaugh, Q. Zhang, Low voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98, 2095–2110 (2010)

  7. 7.

    O.M. Nayfeh, J.L. Hoyt, D.A. Antoniadis, Strained-Si1- xGex/Si band-to-band tunneling transistors: impact of tunnel junction germanium composition and doping concentration on switching behavior. IEEE Trans. Electron Devices 56, 2264–2269 (2009)

  8. 8.

    K.-H. Kao, A.S. Verhulst, W.G. Vandenberghe, B. Sorée, G. Groeseneken, K.D. Meyer, Direct and indirect band-to-band tunneling in germanium-based TFETs. IEEE Trans. Electron Devices 59, 292–301 (2012)

  9. 9.

    N.D. Chien, C.H. Shih, L.T. Vinh, Drive current enhancement in tunnel field-effect transistors by graded heterojunction approach. J. Appl. Phys. 114, 094507 (2013)

  10. 10.

    N.D. Chien, C.-H. Shih, Oxide thickness-dependent effects of source doping profile on the performance of single- and double-gate tunnel field-effect transistors. Superlattices Microstruct. 102, 284–299 (2017)

  11. 11.

    C. Anghel, P. Chilagani, A. Amara, A. Vladimirescu, Tunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric. Appl. Phys. Lett. 96, 122104 (2010)

  12. 12.

    S.L. Noor, S. Safa, M.D.Z.R. Khan, A silicon-based dual-material double-gate tunnel field-effect transistor with optimized performance. Int. J. Numer. Model. Electron Netw. Devices Fields 30, e2220 (2017)

  13. 13.

    E.-H. Toh, G.H. Wang, L. Chan, G. Samudra, Y.-C. Yeo, Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization. Appl. Phys. Lett. 90, 263507 (2007)

  14. 14.

    D. Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, V. Narayanan, A. Liu, D. Loubychev, J. Fastenau, S. Datta, Experimental staggered-source and N+ pocket-doped channel III–V tunnel field-effect transistors and their scalabilities. Appl. Phys. Exp. 4, 024105 (2011)

  15. 15.

    W. G. Vandenberghe, A.S. Verhulst, G. Groeseneken, B. Soree, W. Magnus, Analytical model for point and line tunneling in a tunnel field-effect transistor. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 137–140 (2008)

  16. 16.

    N.D. Chien, C.-H. Shih, Short channel effects in tunnel field-effect transistors with different configurations of abrupt and graded Si/SiGe heterojunctions. Superlattices Microstruct. 100, 857–866 (2016)

  17. 17.

    N.D. Chien, C. H. Shih, Y. H. Chen, N.T. Thu, Different scalabilities of N- and P-type tunnel field-effect transistors with Si/SiGe heterojunctions. International Conference on Electronics, Information and Communications (ICEIC), 10–13 (2016)

  18. 18.

    K. Boucart, A.M. Ionescu, Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans. Electron Devices 54, 1725–1733 (2007)

  19. 19.

    W.-Y. Choi, W. Lee, Hetero-gate-dielectric tunneling field-effect transistors. IEEE Trans. Electron Devices 57, 2317–2319 (2010)

  20. 20.

    W.-Y. Choi, H.K. Lee, Demonstration of hetero-gate-dielectric tunneling field-effect transistors. Nano Converg. 3, 1–15 (2016)

  21. 21.

    M.J. Lee, W.-Y. Choi, Effects of device geometry on hetero-gate-dielectric tunneling field-effect transistors. IEEE Electron Device Lett. 33, 1459–1461 (2012)

  22. 22.

    J. Madan, R. Chaujar, Gate drain-overlapped-asymmetric gate dielectric-GAA-TFET: a solution for suppressed ambipolarity and enhanced on state behavior. Appl. Phys. A 122, 973 (2016)

  23. 23.

    A. Pon, A.S. Carmel, A. Bhattacharyya, R. Ramesh, Performance analysis of asymmetric dielectric modulated dual short gate tunnel field effect transistor. Superlattices Microstruct. 113, 608–615 (2017)

  24. 24.

    2013 Synopsys MEDICI User’s manual (California: Synopsys Inc.)

  25. 25.

    C.-H. Shih, N.D. Chien, Design and modeling of line-tunneling field-effect transistors using low-bandgap semiconductors. IEEE Trans. Electron Devices 61, 1907–1913 (2014)

  26. 26.

    E.O. Kane, Theory of tunneling. J. Appl. Phys. 31, 83–91 (1961)

  27. 27.

    Q. Smet et al., InGaAs tunnel diodes for the calibration of semi-classical and quantum mechanical band-to-band tunneling models. J. Appl. Phys. 115, 184503 (2014)

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This research is funded by Vietnam National Foundation for Science and Technology Development (NAFOSTED) under grant number 103.02–2018.309, by the Ministry of Education and Training of Vietnam and Dalat University under project code B2019-DLA-05. This work is also supported by the Ministry of Science and Technology and the National Center for High-Performance Computing of Taiwan.

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Correspondence to Nguyen Dang Chien.

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Shih, C., Chien, N.D., Tran, H. et al. Device physics and design of hetero-gate dielectric tunnel field-effect transistors with different low/high-k EOT ratios. Appl. Phys. A 126, 66 (2020).

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  • Hetero-gate dielectric
  • High-k gate dielectric
  • Band-to-band tunneling
  • Tunnel field-effect transistor