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Applied Physics A

, 125:865 | Cite as

An insight to the performance of vertical super-thin body (VSTB) FET in presence of interface traps and corresponding noise and RF characteristics

  • Kuheli Roy BarmanEmail author
  • Srimanta Baishya
Article
  • 20 Downloads

Abstract

We investigated vertical super-thin body (VSTB) FET performance in presence of different interface (HfO2/Si) trap distributions (uniform and Gaussian) and concentrations using TCAD tools. For trap concentration (TC) of 1013 eV−1 cm−2, the percentage change in on-to-off current ratio (Ion/Ioff) is 93.91% for uniform trap (UT) and 49.8% for Gaussian trap (GT) distribution. For the same TC, subthreshold swing (SS) shows percentage change of 5.1% for UT and 11.41% for GT distribution. Thus, the device performance shows good immunity for TC up to 1013 eV−1 cm−2. However, for TC = 1014 eV−1 cm−2 SS degrades significantly. The influence of traps on the cumulative effect of three noise sources (diffusion + generation–recombination/G–R + flicker) and on individual noise sources (G–R and diffusion) is explained qualitatively at low and high frequencies (f = 1 MHz and 10 GHz). The study shows that the overall noise cannot disturb the device performance at very high frequency. Various radio-frequency (RF) parameters like transconductance (gm), total input capacitance (Cgg), gate-drain capacitance (Cgd), unit-gain cutoff frequency (fT), and gain–bandwidth-product (GBP) are also studied for variation of trap types. For TC = 1014 eV−1 cm−2, the percentage change in fTmax (GBPmax) is − 21.43% (− 8%) for UT and − 22.86% (− 9.6%) for GT distribution.

Notes

Acknowledgements

This work is an outcome of a project under CSIR-EMR-II (Sanction no. 22 (0737)17/EMR-II dated 16th May, 2017), Govt. of India awarded to Electronics and Communication Engineering, NIT Silchar, Silchar 788010, India. The authors would also like to acknowledge Mr. Saurav Roy and Mr. Ravi Singh Kurmvanshi for their aid in proper handling of related software.

References

  1. 1.
    M. Riordan, L. Hodesson, C. Herring, The invention of the transistor. Rev. Mod. Phys. 71, S336–S345 (1999)CrossRefGoogle Scholar
  2. 2.
    K. Han, H. Shin, K. Lee, Analytical drain thermal noise current model valid for deep submicron MOSFETs. IEEE Trans. Electron Devices 51(2), 261–269 (2004).  https://doi.org/10.1109/TED.2003.821708 ADSCrossRefGoogle Scholar
  3. 3.
    R.T. Bühler, R. Giacomini, M.A. Pavanello, J.A. Martino, Fin cross-section shape influence on short channel effects of MuGFETs. J. Integr. Circuits Syst. 7, 137–144 (2012)Google Scholar
  4. 4.
    J.C. Tinoco, J. Alvarado, A.G. Martinez-Lopez, J. Raskin, Impact of extrinsic capacitances on FinFETs RF performance, in 2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Santa Clara, CA, 2012, pp. 73–76. 10.1109/SiRF.2012.6160141Google Scholar
  5. 5.
    T. Skotnicki, J.A. Hutchby, T.-J. King, H.-S.P. Wong, F. Boeuf, The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits Devices Mag. 21(1), 16–26 (2005).  https://doi.org/10.1109/MCD.2005.1388765 CrossRefGoogle Scholar
  6. 6.
    F. Balestra, Silicon-on-Insulator Devices, Wiley Encyclopedia of Electrical and Electronics Engineering, edited by John G. Webster (Wiley, 2014).Google Scholar
  7. 7.
    V. Jaju, V. Dalal, Silicon-on-insulator technology, in EE 530 Advances in MOSFETs, pp. 1–12, 2004.Google Scholar
  8. 8.
    S. Cristoloveanu, Silicon on insulator technologies and devices: from present to future. Solid State Electron. 45(8), 1403–1411 (2001)ADSCrossRefGoogle Scholar
  9. 9.
    X. Zhang, D. Connelly, H. Takeuchi, M. Hytha, R.J. Mears, T.K. Liu, Comparison of SOI versus bulk FinFET technologies for 6T-SRAM voltage scaling at the 7-/8-nm node. IEEE Trans. Electron Devices 64(1), 329–332 (2017).  https://doi.org/10.1109/TED.2016.2626397 ADSCrossRefGoogle Scholar
  10. 10.
    N.P. Maity, R. Maity, S. Maity, S. Baishya, Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation. J. Comput. Electron. 18, 492–499 (2019)CrossRefGoogle Scholar
  11. 11.
    V. Koldiaev, R. Pirogova, Vertical super-thin body semiconductor on dielectric wall devices and methods of their fabrication. U.S. Patent 8 796 085 B2, 2014.Google Scholar
  12. 12.
    C. Riddet, C. Alexander, A.R. Brown, S. Roy, A. Asenov, Simulation of “ab initio” quantum confinement scattering in UTB MOSFETs using three-dimensional ensemble Monte Carlo. IEEE Trans. Electron Devices 58(3), 600–608 (2011).  https://doi.org/10.1109/TED.2010.2095422 ADSCrossRefGoogle Scholar
  13. 13.
    B. Majkusiak, T. Janik, J. Walczak, Semiconductor thickness effects in the double-gate SOI MOSFET. IEEE Trans. Electron Devices 45(5), 1127–1134 (1998)ADSCrossRefGoogle Scholar
  14. 14.
    K. Uchida, J. Koga, S.-I. Takagi, Experimental study on carrier transport mechanisms in double- and single-gate ultrathin-body MOSFETs—Coulomb scattering, volume inversion, and δTSOI-induced scattering, in IEEE International Electron Devices Meeting 2003, Washington, DC, USA, 2003, pp.33.5.1–33.5.4. 10.1109/IEDM.2003.1269402Google Scholar
  15. 15.
    Y. Omura, H. Konishi, K. Yoshimoto, Impact of fin aspect ratio on short-channel control and drivability of multiple-gate SOI MOSFETs. J. Semicond. Technol. Sci 8(4), 302–310 (2008)CrossRefGoogle Scholar
  16. 16.
    Y. Liu, K. Ishii, M. Masahara, T. Tsutsumi, H. Takashima, H. Yamauchi, E. Suzuki, Cross-sectional channel shape dependence of short channel effects in fin-type double-gate metal oxide semiconductor field effect transistors. Jpn. J. Appl. Phys. 43(4S), 2151 (2004)ADSCrossRefGoogle Scholar
  17. 17.
    S. Roy, A. Chatterjee, D.K. Sinha, R. Pirogova, S. Baishya, 2-D analytical modeling of surface potential and threshold voltage for vertical super-thin body FET. IEEE Trans. Electron Devices 64(5), 2106–2112 (2017).  https://doi.org/10.1109/TED.2017.2687465 ADSCrossRefGoogle Scholar
  18. 18.
    G.D. Wilk, R.M. Wallace, J.M. Anthony, High-k gate dielectrics: Current status and materials properties considerations. J. Appl. Phys. 89, 5243–5275 (2001)ADSCrossRefGoogle Scholar
  19. 19.
    S.Y. Tan, Challenge and performance limitations of high-K and oxynitride gate dielectrics for 90/65 nm CMOS technology. Microelectron. J. 38, 783–786 (2007)CrossRefGoogle Scholar
  20. 20.
    M.H. Cho, D.H. Ko, Y.G. Choi, K. Jeong, D.Y. Noh, H.J. Kim, C.N. Whang, Structural and electrical characteristics of Y2O3 films grown on oxidized Si(100) surface. J. Vac. Sci. Technol. A 19, 192–199 (2001)ADSCrossRefGoogle Scholar
  21. 21.
    I. De, D. Johri, A. Srivastava, C.M. Osburn, Impact of gate work function on device performance at the 50 nm technology node. Solid State Electron. 44, 1077–1080 (2000)ADSCrossRefGoogle Scholar
  22. 22.
    R. Jiang, E. Xie, Z. Wang, Interfacial chemical structure of HfO2/Si film fabricated by sputtering. Appl. Phys. Lett. 89(14), 142 907-1–142 907-3 (2006)Google Scholar
  23. 23.
    D. Schmeiser, E. Zschech, Silicate formation at the interface of Hf-oxide as a high-k dielectrics and Si(0 0 1) surfaces. Mater. Sci. Semicond. Process 9, 934–939 (2006)CrossRefGoogle Scholar
  24. 24.
    S.J. Chang, W.C. Lee, J. Hwang, M. Hong, J. Kwo, Time dependent preferential sputtering in the HfO2 layer on Si (100). Thin Solid Films 516, 948–952 (2008)ADSCrossRefGoogle Scholar
  25. 25.
    N. Miyata, Study of direct-contact HfO2/Si interfaces. Materials 5, 512–527 (2012)ADSCrossRefGoogle Scholar
  26. 26.
    N.P. Maity, R. Maity, R.K. Thapa, S. Baishya, Study of interface charge densities for ZrO2 and Hf02 based metal-oxide-semiconductor devices. Adv. Mater. Sci. Eng. 2014, 1–6 (2014)CrossRefGoogle Scholar
  27. 27.
    S.Y. Tan, Control of interface traps in HfO2 gate dielectric on silicon. J. Electron. Mater. 39, 2435–2440 (2010)ADSCrossRefGoogle Scholar
  28. 28.
    R. Goswami, B. Bhowmick, S. Baishya, Electrical noise in circular gate tunnel FET in presence of interface traps. Superlattices Microstruct. 86, 342–354 (2015)ADSCrossRefGoogle Scholar
  29. 29.
    P. Anandan, A. Nithya, N. Mohankumar, Simulation of flicker noise in gate-all-around silicon nanowire MOSFETs including interface traps. Microelectron. Reliab. 54, 2723–2727 (2014)CrossRefGoogle Scholar
  30. 30.
    L.K.J. Vandamme, F.N. Hooge, What do we certainly know about 1/f noise in MOSTs? IEEE Trans. Electron. Devices 55(11), 3070–3085 (2008).  https://doi.org/10.1109/TED.2008.2005167 ADSCrossRefGoogle Scholar
  31. 31.
    S.Y. Wu, Theory of generation–recombination noise in MOS transistors. Solid State Electron. 11, 25–32 (1968)ADSCrossRefGoogle Scholar
  32. 32.
    Sentaurus Device User Manual, Version J 2014.09 (Synopsis Inc., Mountain View, 2014)Google Scholar
  33. 33.
    P. Saha, P. Banerjee, S.K. Sarkar, 2D modeling based comprehensive analysis of short channel effects in DMG strained VSTB FET. Superlattices Microstruct. 118, 16–28 (2018)ADSCrossRefGoogle Scholar
  34. 34.
    International Technology Roadmap for Semiconductors. (2015). [Online]. https://eps.ieee.org/images/files/Roadmap/ITRSFacInt2015.pdf.
  35. 35.
    X. Chen, C.M. Tan, Modeling and analysis of gate-all-around silicon nanowire FET. Microelectron. Reliab. 54, 1103–1108 (2014)CrossRefGoogle Scholar
  36. 36.
    K.R. Barman, S. Baishya, Performance analysis of vertical super-thin body (VSTB) FET and its characteristics in presence of noise. Appl. Phys. A 125, 401 (2019).  https://doi.org/10.1007/s00339-019-2682-x ADSCrossRefGoogle Scholar
  37. 37.
    X.Y. Huang et al., Effect of interface traps and oxide charge on drain current degradation in tunneling field-effect transistors. IEEE Electron Device Lett. 31(8), 779–781 (2010).  https://doi.org/10.1109/LED.2010.2050456 ADSCrossRefGoogle Scholar
  38. 38.
    Y. Eng et al., Importance of ΔV DIBLSS/(I on/I off) in evaluating the performance of n-channel bulk FinFET devices. IEEE J. Electron Devices Soc. 6, 207–213 (2018).  https://doi.org/10.1109/JEDS.2018.2789922 CrossRefGoogle Scholar
  39. 39.
    M. Schlosser, K.K. Bhuwalka, M. Sauter, T. Zilbauer, T. Sulima, I. Eisele, Fringing-induced drain current improvement in the tunnel field-effect transistor with high-к gate dielectrics. IEEE Trans. Electron Devices 56(1), 100–108 (2009).  https://doi.org/10.1109/TED.2008.2008375 ADSCrossRefGoogle Scholar
  40. 40.
    C. Shen, M.-F. Li, H. Yu, X. Wang, Y.-C. Yeo, D. Chan, D.-L. Kwong, Physical model for frequency-dependent dynamic charge trapping in metal oxide-semiconductor field effect transistors with HfO2 gate dielectric. Appl. Phys. Lett. 86, 093510 (2005)ADSCrossRefGoogle Scholar
  41. 41.
    V. Vijayvargiya, S.K. Vishvakarma, Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance. IEEE Trans. Nanotechnol. 13(5), 974–981 (2014).  https://doi.org/10.1109/TNANO.2014.2336812 ADSCrossRefGoogle Scholar
  42. 42.
    KWJ Chew et al., RF performance of 28 nm PolySiON and HKMG CMOS devices, in 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Phoenix, AZ, 2015, pp. 43–46. 10.1109/RFIC.2015.7337700Google Scholar

Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringNational Institute of Technology SilcharSilcharIndia

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