Applied Physics A

, 123:268 | Cite as

Gate-tuned negative differential resistance observed at room temperature in an array of gold nanoparticles

  • Tran Thi Thu Huong
  • Kazuhiko Matsumoto
  • Masataka Moriya
  • Hiroshi Shimada
  • Yasuo Kimura
  • Ayumi Hirano-Iwata
  • Yoshinao Mizugaki
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We fabricated a single-electron (SE) device using gold nanoparticles (Au NPs). Drain, source, and gate electrodes on a SiO\({_2}\)/Si substrate were formed using electron beam lithography (EBL) and thermal evaporation of Au. Subsequently, solutions of 3-nm-diameter and 5-nm-diameter Au NPs were dropped on the device to make current paths through Au NPs among the electrodes. Measurements of the device exhibited negative differential resistance (NDR) in the current–voltage characteristics between the drain and source electrodes at room temperature (298 K). The NDR behavior was tuned by applying a gate voltage.


Gate Voltage Tunnel Junction Electron Beam Lithography Negative Differential Resistance Gate Electrode 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



This work was partly supported by JSPS KAKENHI Grant Number 15K13999 and by CREST, JST.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2017

Authors and Affiliations

  • Tran Thi Thu Huong
    • 1
  • Kazuhiko Matsumoto
    • 1
  • Masataka Moriya
    • 1
  • Hiroshi Shimada
    • 1
  • Yasuo Kimura
    • 2
  • Ayumi Hirano-Iwata
    • 3
  • Yoshinao Mizugaki
    • 1
  1. 1.The University of Electro-CommunicationsChofuJapan
  2. 2.Tokyo University of TechnologyHachiojiJapan
  3. 3.Tohoku UniversitySendaiJapan

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