Applied Physics A

, Volume 95, Issue 1, pp 139–145

Bias stress effect in low-voltage organic thin-film transistors

  • Ute Zschieschang
  • R. Thomas Weitz
  • Klaus Kern
  • Hagen Klauk
Open Access
Article

DOI: 10.1007/s00339-008-5019-8

Cite this article as:
Zschieschang, U., Weitz, R.T., Kern, K. et al. Appl. Phys. A (2009) 95: 139. doi:10.1007/s00339-008-5019-8

Abstract

The bias stress effect in pentacene organic thin-film transistors has been investigated. The transistors utilize a thin gate dielectric based on an organic self-assembled monolayer and thus can be operated at low voltages. The bias stress-induced threshold voltage shift has been analyzed for different drain-source voltages. By fitting the time-dependent threshold voltage shift to a stretched exponential function, both the maximum (equilibrium) threshold voltage shift and the time constant of the threshold voltage shift were determined for each drain-source voltage. It was found that both the equilibrium threshold voltage shift and the time constant decrease significantly with increasing drain-source voltage. This suggests that when a drain-source voltage is applied to the transistor during gate bias stress, the tilting of the HOMO and LUMO bands along the channel creates a pathway for the fast release of trapped carriers.

PACS

71.20.Rv 72.80.Le 73.61.Ph 85.30.Tv 

Copyright information

© The Author(s) 2008

Authors and Affiliations

  • Ute Zschieschang
    • 1
  • R. Thomas Weitz
    • 1
  • Klaus Kern
    • 1
    • 2
  • Hagen Klauk
    • 1
  1. 1.Max Planck Institute for Solid State ResearchStuttgartGermany
  2. 2.Institut de Physique des NanostructuresEcole Polytechnique Fédérale de LausanneLausanneSwitzerland

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