Reactive synthesis with maximum realizability of linear temporal logic specifications


A challenging problem for autonomous systems is to synthesize a reactive controller that conforms to a set of given correctness properties. Linear temporal logic (LTL) provides a formal language to specify the desired behavioral properties of systems. In applications in which the specifications originate from various aspects of the system design, or consist of a large set of formulas, the overall system specification may be unrealizable. Driven by this fact, we develop an optimization variant of synthesis from LTL formulas, where the goal is to design a controller that satisfies a set of hard specifications and minimally violates a set of soft specifications. To that end, we introduce a value function that, by exploiting the LTL semantics, quantifies the level of violation of properties. Inspired by the idea of bounded synthesis, we fix a bound on the implementation size and search for an implementation that is optimal with respect to the said value function. We propose a novel maximum satisfiability encoding of the search for an optimal implementation (within the given bound on the implementation size). We iteratively increase the bound on the implementation size until a termination criterion, such as a threshold over the value function, is met.

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  1. 1.

    Almagor, S., Boker, U., Kupferman, O.: Formally reasoning about quality. J. ACM 63(3), 24:1–24:56 (2016)

  2. 2.

    Alur, R., Kanade, A., Weiss, G.: Ranking automata and games for prioritized requirements. In: Proceedings of International Conference on Computer-Aided Verification, vol. 5123 of LNCS (2008)

  3. 3.

    Baier, C., Katoen, J.: Principles of model checking. MIT press (2008)

  4. 4.

    Berg, J., Hyttinen, A., Järvisalo, M.: Applications of MaxSAT in data analysis. In: Pragmatics of SAT (2015)

  5. 5.

    Biere, A., Heule, M., van Maaren, H.: Handbook of Satisfiability, vol. 185. IOS Press, Amsterdam (2009)

  6. 6.

    Bloem, R., Chatterjee, K., Henzinger, T. A., Jobstmann, B.: Better quality in synthesis through quantitative objectives. In: Proceedings of International Conference on Computer-Aided Verification, vol. 5643 of LNCS, pp. 140–156 (2009)

  7. 7.

    Cimatti, A., Roveri, M., Schuppan, V., Tchaltsev, A.: Diagnostic information for realizability. In: Proceedings of International Conference on Verification, Model Checking, and Abstract Interpretation, LNCS (2008)

  8. 8.

    Cimatti, A., Roveri, M., Schuppan, V., Tonetta, S.: Boolean abstraction for temporal logic satisfiability. In: Proceedings of International Conference on Computer-Aided Verification, vol. 4590 of LNCS, pp. 532–546 (2007)

  9. 9.

    Dimitrova, R., Ghasemi, M., Topcu, U.: Maximum realizability for linear temporal logic specifications. In: Proceedings of Automated Technology for Verification and Analysis, pp. 458–475. Springer (2018)

  10. 10.

    Duret-Lutz, A., Lewkowicz, A., Fauchille, A., Michaud, T., Renault, E., Xu, L.: Spot 2.0—a framework for LTL and \(\omega \)-automata manipulation. In: Proceedings of Automated Technology for Verification and Analysis, vol. 9938 of LNCS (2016)

  11. 11.

    Ehlers, R., Raman, V.: Low-effort specification debugging and analysis. In: Proceedings of Workshop on Synthesis, vol. 157 of EPTCS, pp. 117–133 (2014)

  12. 12.

    Faymonville, P., Finkbeiner, B., Rabe, M. N., Tentrup, L.: Encodings of bounded synthesis. In: Proceedings of International Conference on Tools and Algorithms for the Construction and Analysis of Systems, vol. 10205 of LNCS, pp. 354–370 (2017)

  13. 13.

    Finkbeiner, B., Schewe, S.: Bounded synthesis. Int. J. Softw. Tools Technol. Transf. 15(5–6), 519–539 (2013)

  14. 14.

    Janota, M., Lynce, I., Manquinho, V., Marques-Silva, J.: PackUp: tools for package upgradability solving. J. Satisf. Boolean Model. Comput. 8, 89–94 (2012)

  15. 15.

    Juma, F., Hsu, E. I., McIlraith, S. A.: Preference-based planning via MaxSAT. In: Proceedings of Advances in Artificial Intelligence, vol. 7310 of LNCS, pp. 109–120 (2012)

  16. 16.

    Kim, K., Fainekos, G. E., Sankaranarayanan, S.: On the minimal revision problem of specification automata. International Journal of Robotics Research 34(12), 1515-1535 (2015)

  17. 17.

    Kupferman, O., Vardi, M. Y.: Safraless decision procedures. In: Proceedings of IEEE Annual Symposium on Foundations of Computer Science, pp. 531–542 (2005)

  18. 18.

    Kupferman, O., Vardi, M.Y.: Model checking of safety properties. Form. Methods Syst. Des. 19(3), 291–314 (2001)

  19. 19.

    Lahijanian, M., Almagor, S., Fried, D., Kavraki, L. E., Vardi, M. Y.: This time the robot settles for a cost: a quantitative approach to temporal logic planning with partial satisfaction. In: Proceedings of Association for the Advancement of Artificial Intelligence (2015)

  20. 20.

    Lahijanian, M., Kwiatkowska, M. Z.: Specification revision for Markov decision processes with optimal trade-off. In: Proceedings of IEEE Conference on Decision and Control, pp. 7411–7418, (2016)

  21. 21.

    Lahijanian, M., Maly, M.R., Fried, D., Kavraki, L.E., Kress-Gazit, H., Vardi, M.Y.: Iterative temporal planning in uncertain environments with partial satisfaction guarantees. IEEE Trans. Robot. 32(3), 583–599 (2016)

  22. 22.

    Martins, R., Manquinho, V. M., Lynce, I.: Open-WBO: a modular MaxSAT solver. In: Proceedings of SAT’14, vol. 8561 of LNCS, pp. 438–445 (2014)

  23. 23.

    Park, J. D.: Using weighted MAX-SAT engines to solve MPE. In: Proceedings of American Association for Artificial Intelligence, pp. 682–687 (2002)

  24. 24.

    Pnueli, A.: The temporal logic of programs. In: Annual Symposium on Foundations of Computer Science, pp. 46–57. IEEE (1977)

  25. 25.

    Raman, V., Kress-Gazit, H.: Towards minimal explanations of unsynthesizability for high-level robot behaviors. In: Proceedings of IEEE/RSJ International Conference on Intelligent Robots and Systems, pp. 757–762 (2013)

  26. 26.

    Robinson, N., Gretton, C., Pham, D. N., Sattar, A.: Partial weighted MaxSAT for optimal planning. In: Proceedings of Pacific rim international conference on artificial intelligence, pp. 231–243. Springer (2010)

  27. 27.

    Schewe, S., Finkbeiner, B.: Bounded synthesis. In: Proceedings of Automated Technology for Verification and Analysis, vol. 4762 of LNCS, pp. 474–488 (2007)

  28. 28.

    Schuppan, V.: Towards a notion of unsatisfiable and unrealizable cores for LTL. Sci. Comput. Program. 77(7–8), 908–939 (2012)

  29. 29.

    Tabuada, P., Neider, D.: Robust linear temporal logic. In: Proceedings of Computer Science Logic, vol. 62 of LIPIcs, pp. 10:1–10:21 (2016)

  30. 30.

    Tomita, T., Ueno, A., Shimakawa, M., Hagihara, S., Yonezaki, N.: Safraless LTL synthesis considering maximal realizability. Acta Inf. 54(7), 655–692 (2017)

  31. 31.

    Tumova, J., Hall, G. C., Karaman, S., Frazzoli, E., Rus, D.: Least-violating control strategy synthesis with safety rules. In: Proceedings of ACM International Conference on Hybrid Systems: Computation and Control (2013)

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Correspondence to Mahsa Ghasemi.

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Part of the results in this paper were presented at the Sixteenth International Symposium on Automated Technology for Verification and Analysis, Los Angeles, California, USA, October 2018 [9]. This work was supported in part by AFRL Grants UTC 17-S8401-10-C1 and FA8650-15-C-2546, ONR Grant N000141613165, and NASA Grant NNX17AD04G.

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Dimitrova, R., Ghasemi, M. & Topcu, U. Reactive synthesis with maximum realizability of linear temporal logic specifications. Acta Informatica (2019).

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