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Reactive synthesis with maximum realizability of linear temporal logic specifications

Abstract

A challenging problem for autonomous systems is to synthesize a reactive controller that conforms to a set of given correctness properties. Linear temporal logic (LTL) provides a formal language to specify the desired behavioral properties of systems. In applications in which the specifications originate from various aspects of the system design, or consist of a large set of formulas, the overall system specification may be unrealizable. Driven by this fact, we develop an optimization variant of synthesis from LTL formulas, where the goal is to design a controller that satisfies a set of hard specifications and minimally violates a set of soft specifications. To that end, we introduce a value function that, by exploiting the LTL semantics, quantifies the level of violation of properties. Inspired by the idea of bounded synthesis, we fix a bound on the implementation size and search for an implementation that is optimal with respect to the said value function. We propose a novel maximum satisfiability encoding of the search for an optimal implementation (within the given bound on the implementation size). We iteratively increase the bound on the implementation size until a termination criterion, such as a threshold over the value function, is met.

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Notes

  1. 1.

    The code is available at https://github.com/MahsaGhasemi/max-realizability.

  2. 2.

    There can be different indices i for which \(e_i = p\) at the same time. While this will be redundant, it does not affect the encoding.

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Correspondence to Mahsa Ghasemi.

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Part of the results in this paper were presented at the Sixteenth International Symposium on Automated Technology for Verification and Analysis, Los Angeles, California, USA, October 2018 [9]. This work was supported in part by AFRL Grants UTC 17-S8401-10-C1 and FA8650-15-C-2546, ONR Grant N000141613165, and NASA Grant NNX17AD04G.

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Dimitrova, R., Ghasemi, M. & Topcu, U. Reactive synthesis with maximum realizability of linear temporal logic specifications. Acta Informatica (2019). https://doi.org/10.1007/s00236-019-00348-4

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