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Optimization of 3D IC stacking chip on molded encapsulation process: a response surface methodology approach

  • M. H. H. Ishak
  • Farzad IsmailEmail author
  • M. S. Abdul Aziz
  • M. Z. Abdullah
  • Aizat Abas
ORIGINAL ARTICLE
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Abstract

The stress concentration and deformation of the 3D stacked IC structures can be minimized with an optimal design of the integrated circuit (IC) using a response surface methodology. The geometrical and process parameters (i.e., A = inlet pressure, B = solder bump standoff height, C = chip thickness, and D = aspect ratio) were optimized via a central composite design (CCD) for the molded encapsulation process. The fluid/structure interaction (FSI) aspects were considered in the optimization of the molded encapsulation process. The separate effects of the independent variables and their interactions were studied. The calculated empirical models were carried out and well validated with the simulation results. The optimum geometrical and process parameters of the 3D stacked IC package with perimeter solder bump arrangement were characterized as follows: inlet condition of 3.65 MPa, 150 μm of solder bump standoff height, 250 μm of chip thickness, and 2.1 of aspect ratio. The outcomes herein may significantly contribute to the advancement of microelectronic industries.

Keywords

Integrated circuit (IC) encapsulation Fluid structure interaction (FSI) Response surface methodology (RSM) Central composite design (CCD) 

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Notes

Funding information

The Universiti Sains Malaysia (Grant No 1001.PAERO.8014091) provided financial and technical support for this research.

References

  1. 1.
    Lau CS, Abdullah MZ, Che Ani F (2012) Optimization modeling of the cooling stage of reflow soldering process for ball grid array package using the gray-based Taguchi method. Microelectron Reliab 52:1143–1152CrossRefGoogle Scholar
  2. 2.
    Tsai J-T, Chang C-C, Chen W-P, Chou J-H (2016) Optimal parameter design for IC wire bonding process by using fuzzy logic and Taguchi method. IEEE Access 4:3034–3045CrossRefGoogle Scholar
  3. 3.
    Martinek P, Krammer O (2018) Optimising pin-in-paste technology using gradient boosted decision trees. Solder Surf Mt Technol 30:164–170CrossRefGoogle Scholar
  4. 4.
    (Tony) Hou T-H, Su C-H, Chang H-Z (2008) Using neural networks and immune algorithms to find the optimal parameters for an IC wire bonding process. Expert Syst Appl 34:427–436CrossRefGoogle Scholar
  5. 5.
    Hung YH (2009) A neural network classifier with rough set-based feature selection to classify multiclass IC package products. Adv Eng Inform 23:348–357CrossRefGoogle Scholar
  6. 6.
    Chiang T-L, Su C-T (2003) Optimization of TQFP molding process using neuro-fuzzy-GA approach. Eur J Oper Res 147:156–164CrossRefzbMATHGoogle Scholar
  7. 7.
    Khor CY, Abdullah MZ (2012) Optimization of IC encapsulation considering fluid/structure interaction using response surface methodology. Simul Model Pract Theory 29:109–122CrossRefGoogle Scholar
  8. 8.
    Abdul Aziz MS, Abdullah MZ, Khor CY, Azid IA (2015) Optimization of pin through hole connector in thermal fluid-structure interaction analysis of wave soldering process using response surface methodology. Simul Model Pract Theory 57:45–57CrossRefGoogle Scholar
  9. 9.
    Box GEP, Wilson KB (1951) On the experimental attainment of optimum conditions. J R Stat Soc Ser B 13:1–45MathSciNetzbMATHGoogle Scholar
  10. 10.
    Alvarez LF (2000) Approximation model building for design optimization using the response surface methodology and genetic programming. University of BradfordGoogle Scholar
  11. 11.
    van Driel WD, Mavinkurve A, van Gils MAJ, Zhang GQ (2007) Advanced structural similarity rules for the BGA package family. Microelectron Reliab 47:205–214CrossRefGoogle Scholar
  12. 12.
    Leong WC, Abdullah MZ, Khor CY (2013) Optimization of flexible printed circuit board electronics in the flow environment using response surface methodology. Microelectron Reliab 53:1996–2004CrossRefGoogle Scholar
  13. 13.
    Chou C-S, Chen C-Y, Lu W-H, Wu C-J (2015) Optimum conditions of molding VFBGA chips with very minimal gold wire damage using the Taguchi methods. Mater Sci Semicond Process 34:297–304CrossRefGoogle Scholar
  14. 14.
    Karhan Ö, Ceran ÖB, Şara ON, Şimşek B (2017) Response surface methodology based desirability function approach to investigate optimal mixture ratio of silver nanoparticles synthesis process. Ind Eng Chem Res 56:8180–8189CrossRefGoogle Scholar
  15. 15.
    Chen C, Suhling JC, Lall P (2018) Improved submodeling finite element simulation strategies for BGA packages subjected to thermal cycling. In: 2018 17th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm). pp 1146–1154Google Scholar
  16. 16.
    Ishak MHH, Abdullah MZ, Aziz MSA, Saad AA, Abdullah MK, Loh WK, Ooi RC, Ooi CK (2017) Study on the fluid–structure interaction at different layout of stacked chip in molded packaging. Arab J Sci Eng 42:4743–4757CrossRefGoogle Scholar
  17. 17.
    Ishak MHH, Abdullah MZ, Abdul Aziz MS, Abas A, Loh WK, Ooi RC, Ooi CK (2017) Effects of aspect ratio in moulded packaging considering fluid/structure interaction: a CFD modelling approach. J Appl Fluid Mech 10:1799–1811Google Scholar
  18. 18.
    Khor CY, Abdullah MZ, Che Ani F (2011) Study on the fluid/structure interaction at different inlet pressures in molded packaging. Microelectron Eng 88:3182–3194CrossRefGoogle Scholar
  19. 19.
    Abas A, Ishak MHH, Abdullah MZ, Che Ani F, Khor SF (2015) Lattice Boltzmann method study of bga bump arrangements on void formation. Microelectron Reliab 56:170–181CrossRefGoogle Scholar
  20. 20.
    Abas A, Gan ZL, Ishak MHH, Abdullah MZ, Khor SF (2016) Lattice Boltzmann method of different BGA orientations on I-type dispensing method. PLoS One 11:e0159357CrossRefGoogle Scholar
  21. 21.
    Hirt C, Nichols B (1981) Volume of fluid (VOF) method for the dynamics of free boundaries. J Comput Phys 39:201–225CrossRefzbMATHGoogle Scholar
  22. 22.
    Nguyen L, Quentin C, Lee W, Bayyuk S, Bidstrup-Allen SA, Wang S-T (2000) Computational modeling and validation of the encapsulation of plastic packages by transfer molding. J Electron Packag 122:138CrossRefGoogle Scholar
  23. 23.
    Yang HQ, Bayyuk SA, Nguyen LT (1997) Time-accurate, 3-D computation of wire sweep during plasticencapsulation of IC components. 1997 Proc 47th Electron Components Technol Conf 831–836Google Scholar
  24. 24.
    Chang RY, Yang WH, Hwang SJ, Su F (2004) Three-dimensional modeling of mold filling in microelectronics encapsulation process. IEEE Trans Components Packag Technol 27:200–209CrossRefGoogle Scholar
  25. 25.
    Khor CY, Abdullah MZ, Ariff ZM, Leong WC (2012) Effect of stacking chips and inlet positions on void formation in the encapsulation of 3D stacked flip-chip package. Int Commun Heat Mass Transf 39:670–680CrossRefGoogle Scholar
  26. 26.
    Ramdan D, Abdullah MZ, Yusop NM (2012) Effects of outlet vent arrangement on air traps in stacked-chip scale package encapsulation. Int Commun Heat Mass Transf 39:405–413CrossRefGoogle Scholar
  27. 27.
    Shen YK, Ju CM, Shie YJ, Chien HW (2004) Resin flow characteristics of underfill process on flip chip encapsulation. Int Commun Heat Mass Transf 31:1075–1084CrossRefGoogle Scholar
  28. 28.
    Green AE, Zerna W (2002) Theoretical Elasticity. Dover PublicationsGoogle Scholar
  29. 29.
    Ishak MHH, Abdullah MZ, Abdullah MK, Abdul Aziz A, Loh WK, Ooi RC, Ooi CK (2015) FSI analysis of the effect of aspect ratio of stacked chip in encapsulation process of moulded underfill packaging. Appl Mech Mater 786:361–366CrossRefGoogle Scholar
  30. 30.
    Khor CY, Abdullah MK, Abdullah MZ, Abdul Mujeebu M, Ramdan D, Majid MFM a, Ariff ZM (2010) Effect of vertical stacking dies on flow behavior of epoxy molding compound during encapsulation of stacked-chip scale packages. Heat Mass Transf und Stoffuebertragung 46:1315–1325CrossRefGoogle Scholar
  31. 31.
    Khor CY, Abdullah MZ, Abdul Mujeebu M, Che Ani F (2010) FVM based numerical study on the effect of solder bump arrangement on capillary driven flip chip underfill process. Int Commun Heat Mass Transf 37:281–286CrossRefGoogle Scholar
  32. 32.
    Ramdan D, Abdullah ZM, Mujeebu MA, Loh WK, Ooi CK, Ooi RC (2012) FSI simulation of wire sweep PBGA encapsulation process considering rheology effect. Components, Packag Manuf Technol IEEE Trans 2:593–603CrossRefGoogle Scholar
  33. 33.
    Wen S, Liu X, Noel Calata J, Lu G, Bai JG (2004) Strategies for improving the reliability of solder joints on power semiconductor devices. Solder Surf Mt Technol 16:27–40Google Scholar
  34. 34.
    Tay AAO, Lin TY (1998) Influence of temperature, humidity and defect location on delamination in plastic IC packages. Therm. Thermomechanical Phenom. Electron. Syst. 1998. ITHERM ’98. Sixth Intersoc. Conf. 179–184Google Scholar

Copyright information

© Springer-Verlag London Ltd., part of Springer Nature 2019

Authors and Affiliations

  • M. H. H. Ishak
    • 1
  • Farzad Ismail
    • 1
    Email author
  • M. S. Abdul Aziz
    • 2
  • M. Z. Abdullah
    • 2
  • Aizat Abas
    • 2
  1. 1.School of Aerospace EngineeringUniversiti Sains Malaysia, Engineering CampusNibong TebalMalaysia
  2. 2.School of Mechanical EngineeringUniversiti Sains Malaysia, Engineering CampusNibong TebalMalaysia

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