Formal Aspects of Computing

, Volume 19, Issue 3, pp 343–362 | Cite as

Proof producing synthesis of arithmetic and cryptographic hardware

  • Konrad Slind
  • Scott Owens
  • Juliano Iyoda
  • Mike Gordon
Original Article


A compiler from a synthesisable subset of higher order logic to clocked synchronous hardware is described. It is being used to create coprocessors for cryptographic and arithmetic applications. The compiler automatically translates a function f defined in higher order logic (typically using recursion) into a device that computes f via a four-phase handshake circuit. Compilation is by fully automatic proof in the HOL4 system, and generates a correctness theorem for each compiled function. Synthesised circuits can be directly translated to Verilog, and then input to design automation tools. A fully-expansive ‘LCF methodology’ allows users to safely modify and extend the compiler’s theorem proving scripts to add optimisations or to enlarge the synthesisable subset of higher order logic.


Theorem proving Compiling Hardware synthesis Cryptography High assurance 


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Copyright information

© British Computer Society 2007

Authors and Affiliations

  • Konrad Slind
    • 1
  • Scott Owens
    • 1
  • Juliano Iyoda
    • 2
  • Mike Gordon
    • 2
  1. 1.School of ComputingUniversity of UtahSalt Lake CityUSA
  2. 2.University of Cambridge Computer LaboratoryCambridgeUK

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