From Physical to Stochastic Modeling of a TEROBased TRNG
Abstract
Security in random number generation for cryptography is closely related to the entropy rate at the generator output. This rate has to be evaluated using an appropriate stochastic model. The stochastic model proposed in this paper is dedicated to the transition effect ring oscillator (TERO)based true random number generator (TRNG) proposed by Varchola and Drutarovsky (in: Cryptographic hardware and embedded systems (CHES), 2010, Springer, 2010). The advantage and originality of this model are that it is derived from a physical model based on a detailed study and on the precise electrical description of the noisy physical phenomena that contribute to the generation of random numbers. We compare the proposed electrical description with data generated in two different technologies: TERO TRNG implementations in 40 and 28 nm CMOS ASICs. Our experimental results are in very good agreement with those obtained with both the physical model of TERO’s noisy behavior and the stochastic model of the TERO TRNG, which we also confirmed using the AIS 31 test suites.
Keywords
Hardware random number generators Transition effect ring oscillator Stochastic models Entropy Statistical tests1 Introduction
Random number generation is a critical issue in most cryptographic applications. Random numbers are used not only as confidential keys, but also as initialization vectors, challenges, nonces, and random masks in sidechannel attack countermeasures. A security flaw in random number generation has a direct impact on the security of the whole cryptographic system. Unlike generators used in Monte Carlo simulations and telecommunications, those designed for cryptography must generate unpredictable random numbers—having perfect statistical properties is necessary but not sufficient.
There are two main categories of random number generators: deterministic random number generators (DRNG) and true random number generators (TRNG), which can be physical (PTRNG) or nonphysical (NPTRNG). While deterministic generators are based on algorithmic processes and are thus not truly random, TRNGs exploit an unpredictable process, such as analog phenomena in electronic devices, to produce a random binary sequence or a sequence of random numbers. The unpredictability of DRNGs is guaranteed computationally and that of TRNGs is guaranteed physically. A good knowledge of the physical process underlying TRNG, which ensures its randomness and hence its unpredictability, is therefore necessary.
The statistical quality of TRNGs and DRNGs is usually evaluated using statistical test suites such as the one first proposed by George Marsaglia [8] and extended by NIST [10]. The goal of these suites is to detect statistical weaknesses such as nonuniformity or the appearance of patterns in a generated random sequence of only limited size. In no case can these tests guarantee the unpredictability of the random binary sequence.
As summarized by Fischer [3], the best way to evaluate unpredictability is to carefully estimate the entropy rate at the generator output. The estimation of entropy must be based on a carefully constructed stochastic model of the random number generation process. The stochastic model is a mathematical construct, which specifies the family of probability distributions that contains all possible distributions of the generated random numbers [7]. In a PTRNG design, the model consists of a mathematical description of a link between the variations in the exploited unpredictable analog phenomena and the variations in the random binary sequence.
The main objective of using a stochastic model is to characterize the probability that an output bit is equal to one, and/or the probability that an nbit output vector features a pattern of some sort. If the variables characterized by these probabilities are independent and identically distributed (IID), the entropy rate can be estimated from their distribution. If the variables are not IID, a conditional entropy rate based on conditional probabilities is usually computed [6].
Estimating entropy using an underlying stochastic model is mandatory in the security certification process, specially at high levels of security [7]. Stochastic models are reasonably easy to construct, but it is sometimes difficult or even impossible to check all the underlying physical assumptions. A physical model could serve as a basis for validation of these assumptions, but it is much more difficult to construct and a detailed knowledge of contributing physical phenomena is necessary.
Our objective was to model the generator recently proposed by Varchola and Drutarovsky [13], which uses a socalled transient effect ring oscillator (TERO) as a source of randomness. We chose this generator because it is small and easy to implement in logic devices, and because it produces good statistical results. However, a satisfactory stochastic model is not yet available for this generator.
The generic stochastic model from [6] was clearly not suitable for the TERObased TRNG. Neither were stochastic models dedicated to other existing generators, like the one proposed for the elementary ring oscillatorbased TRNG in [1], nor that proposed in [12] for the TRNG using many oscillating rings as sources of randomness, nor the one proposed in [2] for the PLLbased TRNG. The models dedicated to structures with transient oscillations, which were proposed in [13] and [5], assume the distribution of generated random numbers to be Gaussian. This assumption disagreed with our own experience and even with the graphs presented in the original paper proposing TERO TRNG [13, p. 8].
For practical reasons—we had only a small number of samples, in which the TERO TRNG was implemented as an independent circuitry inside two complex logic devices, at our disposal—we could not study the design repeatability issues of the TERO TRNG architecture depending on manufacturing process conditions. Our main objective was thus to validate the proposed model and to study variation of model parameters across two different ASIC technologies at various operating conditions.
Our contributions (1) We propose and validate a novel physical TERO model including electric noises that serve as sources of randomness for a given instance of a TERObased TRNG implemented in ASIC. (2) From the physical model, we derive a TERO stochastic model. (3) From the TERO model, we propose and validate a stochastic model of a complete TERObased TRNG and illustrate the use of this model to estimate the entropy rate in conjunction with the output bit rate.
Organization of the paper In Sect. 2, we describe the structure of the TERO and its use in a PTRNG. In Sect. 3, we present implementation of the TERO structure and corresponding TRNG in ASIC. The physical (electrical) and derived stochastic models of the TERO are detailed in Sect. 4. The stochastic model of the complete TERObased TRNG is presented in Sect. 5. In Sect. 6, the effect of temperature and voltage variations on the TERObased TRNG and on the model parameters is studied. We conclude the paper in Sect. 7 by a discussion concerning the relationship between the entropy rate and the output bit rate that can be set up using the proposed stochastic model.
2 TEROBased RNG
TERO is an electronic circuit that oscillates temporarily. It is composed of two control gates that restart temporary oscillations and an even number of inverting logic gates connected in a loop. The number of inverting gates in the loop must be even; otherwise, oscillations would continue permanently like in standard ring oscillators.
Figure 1b presents traces of the \(V_{\mathrm{ctr}}\) input and \(V_{\mathrm{out}1}\) output signal captured from oscilloscope. Following the rising edge of the \(V_{\mathrm{ctr}}\) input, the outputs \(V_{\mathrm{out}1}\) and \(V_{\mathrm{out}2}\) start to oscillate: two rising edges start to propagate in the TERO cell in two opposite directions, and after traversing the NAND gate at the end of the branch, they are transformed into two falling edges, etc. Consequently, to enter the oscillatory state, the number of inverters in each branch of the TERO cell before the NAND gate must be even. Note that this condition is fulfilled automatically in the structure presented in the right panel in Fig. 1a, since each buffer present in this structure is realized in logic devices using a couple of inverters.
The oscillations obtained have a constant mean frequency, but their duty cycle varies over time: it changes monotonously, and after a certain number of periods, it reaches the rate of either 0 or \(100 \%\). At this point, outputs \(V_{\mathrm{out}1}\) and \(V_{\mathrm{out}2}\) stop oscillating and remain stable at two opposite logic values.
The three zooms in Fig. 1b show the changing duty cycle: immediately after the rising edge of the \(V_{\mathrm{ctr}}\) signal, it is close to \(50 \%\) and then decreases until it reaches \(0 \%\). Consequently, signal \(V_{\mathrm{out}1}\) stabilizes at logic level 1. Of course, the signal \(V_{\mathrm{out}2}\) behaves in the opposite way with respect to the duty cycle and stabilizes at logic level 0.
The number of oscillations before the outputs stabilize is not constant but varies because it is impacted by the electronic noises that disturb the normal behavior of transistors in the TERO structure.
3 Implementation of the TERO RNG in ASIC
We implemented TERO in two of STMicroelectronics CMOS processes, with 40 and 28 nm minimum features, respectively. In order to explore the design space, we made the delays in the two TERO branches programmable, each in 64 linear steps (see Fig. 3). Each step consists of one elementary noninverting buffer.
In the 40 nm process, the delays were programmable from 1.6 to 8 ns in 64 regularly spaced steps, resulting in oscillation frequencies in the range of 60–330 MHz. In the 28 nm process, the delays were programmable from 0.6 to 3.3 ns, resulting in oscillation frequencies in the range of 150–900 MHz. The number of oscillations was counted by a 16bit counter.
A particularly tricky issue in the physical layout consists of accounting for the routing delays, which, in such rapid processes, often dominate over the buffer delays. The multiplexers and the two NAND gates themselves add delays that also have be taken in consideration. So routing among the various multiplexers in the oscillation loop must be such that the overall delay in each of the 2 branches increases monotonously when the number of buffers increases from 1 to 64. This requires a careful layout as well as postlayout simulations to guarantee the monotonicity.
This extra burden is only necessary when designing characterization chips. In the final design, the delays should be fixed, or with only a few adjustment steps. Nevertheless, the layout should always be undertaken with great care to control the delays as much as possible.
3.1 Implementation Results

When \(\tau _1\) and \(\tau _2\) are adjusted to the same value, the number of oscillations is usually extremely high, sometimes infinite (i.e., the oscillation never ends). This is of course not suitable in TRNG design. Values in which the delays differ by only 1 to 3 units (number of buffers) should also be avoided, as they are too close to infinite oscillation.

When \(\tau _1\) and \(\tau _2\) are too different, the average number of oscillations is quite small (less than 30), usually resulting in a low entropy rate (because of a too weak jitter accumulation). This too should be avoided.
Figure 4 shows distributions of the 8 million counter values obtained from ASIC devices in four different TERO configurations: two in the 40 nm technology (Fig. 4a, b) and two in the 28 nm technology (Fig. 4c, d). In Fig. 4a, the relative difference between the two TERO branches was 31%; in Fig. 4b, it was 35%; in Fig. 4c, it was 20%; and in Fig. 4d it was 32%. The differences between the TERO branches were obtained using the digital configurable delay chain depicted in Fig. 3.
Before proceeding with the construction of the physical and stochastic models, we tested the statistical quality of the generated bit streams. The bit streams obtained by successive concatenation of the least significant bits constituted the raw binary streams, which were then tested using the AIS 31 protocol [KS11]. The data not only successfully passed all the tests of Procedure B, but also those of Procedure A aimed at testing the postprocessed signals. This means that the generator is suitable for certification according to AIS 31 for PTG.1 and PTG.2 levels even without postprocessing.
These good results are mitigated by the fact that they rely on accurate delay adjustments, which may not be compatible with large volume production. Extensive characterization is still needed to validate TERO usability in industrial contexts.
As explained above, successful evaluation of the output of the generator using statistical tests is a necessary but not sufficient condition to ensure the unpredictability of the generated numbers. The only way to guarantee such a property is to show the link between variations in the distribution of the raw random binary sequence and the physical phenomena that are considered as random, unpredictable, and nonmanipulable. Statistical modeling of underlying analog and digital processes should make it possible to quantify the uncertainty included in the generated random sequence by estimating the entropy rate in this sequence.
4 Physical and Stochastic Models of TERO
4.1 Modeling the Number of Temporary Oscillations
Our study was based on an existing physical model of RS latches published by Reyneri et al. [9]. We completed the noise free model proposed by Reyneri et al. by taking electric noises into account.
4.1.1 Modeling an Ideal NoiseFree Inverter

A comparator, which outputs \(V_{\mathrm{CC}}\) if the input voltage \(V_{\mathrm{in}}\) is smaller than \((V_{\mathrm{CC}}+V_{\mathrm{GND}})/2\); otherwise, it outputs \(V_{\mathrm{GND}}\);

A delay line, which delays comparator output signal by a static delay \(T_{1}\);

A slope limiter, which follows the delay line and generates the output signal \(V_{\mathrm{out}}\).
First, let we consider that the inverter input signal \(V_{\mathrm{in}}\) has a linear form as presented in Fig. 5. We suppose that at \(t=t_{\uparrow }\), signal \(V_{\mathrm{in}}\) goes up from \(V_{\mathrm{GND}}\) to \(V_{\mathrm{CC}}\) and \(\overline{t_{a}}\) is the time at which the output signal \(V_\mathrm{out}\) is equal to \((V_{\mathrm{CC}}+V_{\mathrm{GND}})/2\). At time \(t=t_{\downarrow }\), signal \(V_{\mathrm{in}}\) goes down from \(V_{\mathrm{CC}}\) to \(V_{\mathrm{GND}}\)^{3} and at \(\overline{t_{b}}\) output \(V_\mathrm{out}\) is equal to \((V_{\mathrm{CC}}+V_{\mathrm{GND}})/2\). Consequently, the width of the negative pulse at output \(V_\mathrm{out}\) is equal to \(w_\mathrm{out}= \overline{t_{b}}  \overline{t_{a}}\). The output period signal is finished at \(t=\overline{t_{c}}\), when \(V_{\mathrm{in}}\) goes back to \(V_{\mathrm{CC}}\).
4.1.2 Modeling a Noisy Inverter

f(t) represents an ideal component of the output signal, which contributes to the charge and discharge of the \(C_{L}\) capacitor by noisefree switching currents between the source and drain of output transistors MN and MP;

n(t) corresponds to the noisy component of the output signal, i.e., it contributes to the charge and discharge of the \(C_{L}\) by the noisy signals \(n_{N}\) and \(n_{P}\).
Let us now analyze variations in the width of the pulse transmitted over one inverter as explained earlier in this section, but now in the presence of noisy currents. Let us consider that at \(t=t_{\uparrow }\), signal \(V_{\mathrm{in}}\) goes up from \(V_{\mathrm{GND}}\) to \(V_{\mathrm{CC}}\), and we denote \(t_{a}\) the time, at which the signal \(V_\mathrm{out}\) at the output of the inverter reaches \((V_{\mathrm{CC}}+V_{\mathrm{GND}})/2\). Similarly, at \(t=t_{\downarrow }\), signal \(V_{\mathrm{in}}\) goes down from \(V_{\mathrm{CC}}\) to \(V_{\mathrm{GND}}\) and \(t_{b}\) corresponds to the time at which \(V_\mathrm{out}\) is equal to \((V_{\mathrm{CC}}+V_{\mathrm{GND}})/2\). Finally, at \(t=t_{end}\) signal \(V_{\mathrm{in}}\) goes back to \(V_{VCC}\), ending one cycle. We denote \(t_{c}=t_{end}t_{\uparrow }\) the time that \(V_{\mathrm{in}}\) needs to complete one cycle. For the sake of simplicity, we denote \(w_{\mathrm{in}}\) the width of one (positive) pulse at signal \(V_{\mathrm{in}}\) and \(w_\mathrm{out}\) the corresponding (negative) pulse at the output of an open chain of inverters.
Proofs of the following lemma and propositions are provided in “Appendix A.”
Lemma 1
 1.
\(T_a\sim {\mathcal {N}}\left( \overline{t_a},\,\left( \frac{\sigma }{f'\left( \overline{t_a}\right) }\right) ^2\right) \) and \(T_b\sim {\mathcal {N}}\left( \overline{t_b},\,\left( \frac{\sigma }{f'\left( \overline{t_b}\right) }\right) ^2\right) \)
 2.If \(T_a\) and \(T_b\) are independent,$$\begin{aligned} W_\mathrm{out}\sim {\mathcal {N}}(\mu _\mathrm{out},\,\sigma _\mathrm{out}^2) \text{ with } \left\{ \begin{array}{lcl}\mu _\mathrm{out}&{}=&{}\frac{t_c}{2}+\left( w_{\mathrm{in}}\frac{t_c}{2}\right) (1+H_d)\\ \sigma _\mathrm{out}^2&{}=&{}\sigma ^2\left( \frac{1}{\left( f'\left( \overline{t_a}\right) \right) ^2}+\frac{1}{\left( f'\left( \overline{t_b}\right) \right) ^2}\right) \end{array}\right. \end{aligned}$$
4.1.3 Shortening of the Pulse While it Traverses a Delay Chain
Let us now consider the open chain of N inverters discussed in the previous section, where N is a nonzero positive integer. Let \(V_{\mathrm{in}}\) be the input signal of the first inverter and \(V_{\mathrm{out}_N}\) the output signal of the \(N^{\mathrm{th}}\) inverter. \(W_{\mathrm{out}_N}\) is the width of a pulse at \(V_{\mathrm{out}_N}\) corresponding to a pulse \(w_{\mathrm{in}}\) at signal \(V_{\mathrm{in}}\). The random behavior of \(W_{\mathrm{out}_N}\) is given in Proposition 1.
Proposition 1
4.1.4 Modeling Temporary Oscillations in the TERO Structure
Let us now consider two chains of inverters, as discussed in the previous section. Let \(\{K_{j}\}_{j=1\ldots 2M}\) represent the set of inverters in the first chain and \(\{L_{j}\}_{j=1\ldots 2M^\prime }\) those in the second chain. We denote NK and NL the two NAND gates with outputs \(V_{K}\) and \(V_{L}\). They are connected to chains \(\{K_{j}\}\) and \(\{L_{j}\}\) (as depicted in Fig. 8a) and complete a TERO. If \(V_\mathrm{ctr}\) is equal to \(V_{\mathrm{CC}}\), NK (resp. NL) can be seen as the \(K_{2M+1}^{\mathrm{th}}\) (resp. \(L_{2M^\prime +1}^{\mathrm{th}}\)) inverter of the chain \(K:=\{K_{j}\}_{j=1\ldots 2M+1}\) (resp. \(L:=\{L_{j}\}_{j=1\ldots 2M^\prime +1}\)) generating the mean delay \(\tau _{1}\) (resp. \(\tau _2\)). Theoretically, \(\tau _{1}\) and \(\tau _{2}\) can be identical, if both branches have the same topology. In practice, because of imperfections in the manufacturing process, their values always differ. Without any loss of generality, we can assume that \(\tau _{2}>\tau _{1}\).
At \(t=0\), let signal \(V_\mathrm{ctr}\) go up from \(V_{\mathrm{GND}}\) to \(V_{\mathrm{CC}}\). As shown in Fig 8b, this rising edge forces the outputs of NAND gates NK and NL to fall from \(V_{\mathrm{CC}}\) to \(V_{\mathrm{GND}}\). The falling edge created at \(V_{L}\) (resp. at \(V_{K}\)) propagates over K (resp. L). This creates a pulse of mean width \(\tau _{1}\) (resp. \(\tau _{2}\)) at \(V_{K}\) (resp. \(V_{L}\)).
The two rising edges created on \(V_{K}\) and \(V_{L}\) start to propagate over elements L and K. After a mean delay \(\tau _{2}\) (resp. \(\tau _{1}\)), they cause signal \(V_{K}\) (resp. \(V_{L}\)) to fall from \(V_{\mathrm{CC}}\) to \(V_{\mathrm{GND}}\). The generated signals behave in the same way as the signals traversing set \(\{I_{j}\}\) in the previous section with a cycle of width \(t_c=\tau _1+\tau _2\).
Proposition 2
Let \(\hbox {WK}_{0}\) (resp. \(\hbox {WL}_{0}\)) be the width of the pulse observed at signal \(V_{K}\) (resp. \(V_{L}\)) and \(\hbox {WK}_{S}\) (resp. \(\hbox {WL}_{S}\)) be the pulse width, once it has crossed S times over both sets K and L.
4.2 Experimental Validation of the TERO Stochastic Model
 1.
First, the distribution of temporary oscillations \(N_{\mathrm{OSC}}\) is obtained experimentally.
 2.Equation (6) states that \(\hbox {Pr}\{N_{\mathrm{OSC}} \le q\}=\frac{1}{2}\) for \(q=q_0\), meaning that \(q_0\) is the median of the distribution of temporary oscillations \(N_{\mathrm{OSC}}\):$$\begin{aligned} q_0=\text{ median }(N_{\mathrm{OSC}}). \end{aligned}$$
 3.The probability distribution \(\hbox {Pr}\{N_{\mathrm{OSC}} \le q\}\) can be thus computed for each q:$$\begin{aligned} \hbox {Pr}\{N_{\mathrm{OSC}} \le q\}\approx \frac{\#\{N_{\mathrm{OSC}}\mid N_{\mathrm{OSC}}\le q\}}{\#\{N_{\mathrm{OSC}}\}}. \end{aligned}$$
 4.Then using this approximation, \(Y(q)=erf^{1}\Big (12\hbox {Pr}\{N_{\mathrm{OSC}} \le q\}\Big )\) can be computed. According to Eq. (6), \(erf^{1}\Big (12\hbox {Pr}\{N_{\mathrm{OSC}} \le q\}\Big )=K\frac{1R^{qq_{0}}}{\sqrt{R^{2q}R_M^2 1}}\), soKnowing that \(K=\frac{\sqrt{R^{2}1}}{2\sqrt{2}\sigma _r}\) and \(\sigma _r = \sigma _\mathrm{out}\sqrt{\frac{R^21}{(1+H_d)^21}}/(\tau _{1}+\tau _{2})\), K can be expressed as$$\begin{aligned} Y(q)\approx K\frac{1R^{qq_{0}}}{\sqrt{R^{2q}R_M^2 1}}. \end{aligned}$$and Y(q) as$$\begin{aligned} K=(\tau _1+\tau _2)\frac{\sqrt{(1+H_d)^21}}{2\sqrt{2}\sigma _\mathrm{out}}=(\tau _1+\tau _2)\frac{\sqrt{R^{\frac{1}{M+M^\prime +1}}1}}{2\sqrt{2}\sigma _\mathrm{out}} \end{aligned}$$$$\begin{aligned} Y(q) = \underbrace{\frac{(\tau _1+\tau _2)}{2\sqrt{2}\sigma _\mathrm{out}}}_{K'}\frac{(1R^{qq_{0}})\sqrt{R^{\frac{1}{M+M^\prime +1}}1}}{\sqrt{R^{2q}R_M^2 1}}. \end{aligned}$$(10)
 5.Finally, the value of R is determined. Knowing that \(R \sim 1\) and \(R > 1\), the value \(R_{loop}\), such that the ratio Y(q) / Z(q) is almost constant (i.e., independent from q), is searched in a loop for \(R > 1\) in the neighborhood of 1 . This constant named \(K'\) represents an approximation of the value \(\frac{(\tau _1+\tau _2)}{2\sqrt{2}\sigma _\mathrm{out}}\). As mentioned above, Y(q) was obtained experimentally and Z(q) is derived from Eq. (10) as follows:Then when this particular R and the constant \(K'\) are found, we finally compute the two last parameters of the model$$\begin{aligned} Z(q)=\frac{(1R_{loop}^{qq_{0}})\sqrt{R_{loop}^{\frac{1}{M+M^\prime +1}}1}}{\sqrt{R_{loop}^{2q}R_M^2 1}}. \end{aligned}$$(11)and$$\begin{aligned} \sigma _r=\frac{\sqrt{R^21}}{2\sqrt{2}K'\sqrt{R^{\frac{1}{M+M^\prime +1}}1}} \end{aligned}$$$$\begin{aligned} \varDelta _r=R^{q0}. \end{aligned}$$
In the following section, we will use our model to estimate entropy at the TERO TRNG output.
5 Stochastic Model of the Complete TEROBased TRNG
Model parameters and entropy estimation for the four TERO TRNG configurations featuring histograms from Fig. 4
Technology  ST 40 nm  ST 28 nm  

TERO configuration  (a)  (b)  (c)  (d) 
R  1.01221  1.00701  1.01841  1.01191 
\(\varDelta _r\)  0.3081  0.3531  0.1936  0.3171 
\(\sigma _r\)  0.00205  0.00398  0.00173  0.00615 
\(H_{N_{\mathrm{osc}}}\)  4.801523  6.761983  4.390844  6.423837 
\(H_{b}\)  \(>\,0.9999\)  \(>\,0.9999\)  \(>\,0.9999\)  \(>\,0.9999\) 
As can be seen, in all cases, the entropy rate at the least significant bit was higher than 0.9999, meaning that the entropy per bit exceeded the value required by AIS 31. This was in perfect agreement with the experimental results of the tests AIS 31 presented in Sect. 3.1.
6 Impact of Temperature and Voltage Variations
The measurement results presented in the previous sections have been obtained under nominal operating conditions (voltage and temperature). In the next step, we observed generator output values and variation of the model parameters (\(\sigma _r\), \(\varDelta _r\) and R) in varying conditions. Following our conservative approach, we wished to determine the lower bound of entropy per bit that can be achieved even in the worst case.

\(R=1.01911\),

\(\varDelta _r=0.1506238\),

\(\sigma _r=0.000525218\),

Mean number of oscillations: \(\overline{N}_\mathrm{osc}=126\)
Despite a relative stability of the model parameters and the output entropy rate around the nominal temperature (\(25\,^{\circ }\hbox {C}\)), we could observe that the results and in particular relative delays and transition timings (both rising and falling edges) that are represented by \(\varDelta _r\) and R, respectively, changed slightly with the temperature.
Following the presented conservative approach of entropy estimation, we took the minimum value of the entropy rate per output bit as a low entropy bound for the given implementation. Note that because the entropy rate depends not only on \(\sigma _r\) but also on \(\varDelta _r\) and R, this minimum entropy rate value does not necessarily correspond to the minimum value of \(\sigma _r\).
As can be seen, the supply voltage variation impacts the TERO structure and thus the model parameters more than the temperature variation. The parameter R is not stable around the nominal voltage any more, and it decreases regularly with the increasing voltage. This effect can be explained by the fact that the supply voltage modifies both falling and rising edge times that are modeled globally by the parameter R. Similarly as for temperature variations, we compute the entropy rate per output bit achievable in the worst case.
We could observe in this section that the model parameters are sensitive to environmental changes. These changes should be detected by some dedicated tests that should be embedded in the same device in order to signal significant deviations of security critical parameters caused by deterioration of operating conditions or some attacks.
7 Discussion
As we have seen above, the distribution of counter values for a given instance of the TERObased TRNG is very well characterized by the model parameters R, \(\sigma _r\), and \(\varDelta _r\), and the entropy of the generated sequence depends on this distribution. Using the model, we can observe the impact of the TERO design on the distribution of random numbers and hence on entropy.
First, entropy is determined by relative jitter, i.e., by parameter \(\sigma _r\). Since designers cannot directly alter the sources of thermal noise, they can only change the relative jitter by reducing the delay of the two TERO branches. This corresponds to increasing the frequency of oscillations.
Another important model parameter that determines entropy rate is the relative difference between the two TERO branches, i.e., parameter \(\varDelta _r\). With smaller relative differences, TERO accumulates more jitter because it oscillates longer. As we saw in our TERO TRNG implementations, the entropy rate per generated output byte was over 4.8, 6.7, 4.3, and 6.4, respectively. This means that if the designer only used one bit per generated byte (the counter output), they would be discarding a high percentage of usable random data. Of course, some postprocessing could be used to profit from as much entropy as possible, but it would require additional silicon area, especially if a sophisticated algorithm was used (which would probably be the case in order to maintain a maximum entropy rate).
Another much more practical solution would be to unbalance the two TERO branches to the extent that the entropy rate per generated byte is sufficiently higher than 1 and then to use only one bit per generated number. Because of the difference in delays in the two branches, the TERO would oscillate for a shorter time and the output bit rate would consequently be higher. Since the entropy rate per generated number would be higher than one, each generated bit (the least significant bit of the counter) would have enough entropy and postprocessing would not be necessary.
8 Conclusion
In this paper, we analyzed the processes that transform the noisy currents in the TERO circuitry into a random bit stream of the TERObased TRNG. First, we conducted a detailed analysis of electric processes inside the TERO structure, and based on this analysis, we proposed the physical model of the TERO. We checked the model in four TERO configurations implemented in an ST 40 nm and ST 28 nm ASIC technology.
Next, based on this model, we proposed a stochastic model of a complete TERObased TRNG. We showed that the proposed stochastic model can be successfully used to estimate the entropy rate. The entropy estimations are in perfect agreement with the results of the AIS 31 test suites.
We also showed that the proposed TRNG stochastic model can not only be used to estimate the entropy rate at the output of the generator, but also for entropy management, by setting a sufficient entropy rate while maintaining the maximum output bit rate.
Footnotes
 1.
Denoted \(\varDelta _r\) later on the paper.
 2.
Where \(K_{0}\) is a positive real number smaller than 1.
 3.
\(w_{\mathrm{in}}\) can be defined as \(w_{\mathrm{in}}=t_{\downarrow }t_{\uparrow }\).
 4.
This may be not true at the device startup, but this assumption is reasonable after some time \(t_0\). For each \(t\ge t_0\), we assume that n(t) follows a normal distribution with mean 0 and variance \(\sigma ^2\), denoted \(n(t)\sim {\mathcal {N}}(0,\sigma ^2)\) in the following.
Notes
Acknowledgements
This work received funds from the European ENIAC Joint Undertaking (JU) in the framework of the project TOISE (Trusted Computing for European Embedded Systems) and from the European Union’s Horizon 2020 research and innovation programme in the framework of the project HECTOR (Hardware Enabled Crypto and Randomness) under Grant Agreement No. 644052. The authors wish to thank Nicolas Bruneau, Michel Agoyan, and Yannick Teglia for their help and numerous discussions.
References
 1.M. Baudet, D. Lubicz, J. Micolod, A. Tassiaux, On the security of oscillatorbased random number generators. J. Cryptol. 24(2), 398–425 (2011)MathSciNetCrossRefzbMATHGoogle Scholar
 2.F. Bernard, V. Fischer, B. Valtchanov, Mathematical model of physical RNGs based on coherent sampling. Tatra Mt. Math. Publ. 45(1), 1–14 (2010)MathSciNetzbMATHGoogle Scholar
 3.V. Fischer, A closer look at security in random number generators design, in Constructive SideChannel Analysis and Secure Design—COSADE 2012 (Springer, 2012), pp. 167–182Google Scholar
 4.P. Haddad, Y. Teglia, F. Bernard, V. Fischer, On the assumption of mutual independence of jitter realizations in PTRNG stochastic models, in Proceedings of Design, Automation and Test in Europe DATE 2014 (Dresden, Germany, March 2014), pp. 1–6Google Scholar
 5.L. Hars, Random number generation based on oscillatory metastability in ring circuits. https://eprint.iacr.org/2011/637.pdf (2011)
 6.W. Killmann, W. Schindler, A design for a physical RNG with robust entropy estimators, in Elisabeth Oswald and Pankaj Rohatgi, editors, Cryptographic Hardware and Embedded Systems—CHES 2008, volume 5154 of LNCS (Springer, 2008), pp. 146–163Google Scholar
 7.W. Killmann, W. Schindler, A proposal for: functionality classes for random number generators. https://www.bsi.bund.de (2011)
 8.G. Marsaglia, DIEHARD: Battery of Tests of Randomness. http://stat.fsu.edu/pub/diehard/ (1996)
 9.L.M. Reyneri, D. Del Corso, B. Sacco, Oscillatory metastability in homogeneous and inhomogeneous flipflops. IEEE J. SolidState Circuits 25(1), 254–264 (1990)CrossRefGoogle Scholar
 10.A. Rukhin, J. Soto, J. Nechvatal, M. Smid, E. Barker, S. Leigh, M. Levenson, M. Vangel, D. Banks, A. Heckert, J. Dray, S. Vo, A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications—NIST SP 80022, rev. 1a (2010)Google Scholar
 11.C. Shannon, A mathematical theory of communication. Bell Syst. Tech. J. 27, 379–423, 623–656 July, (1948)Google Scholar
 12.B. Sunar, W.J. Martin, D.R. Stinson, A provably secure true random number generator with builtin tolerance to active attacks. IEEE Trans. Comput. 109–119 (2007)Google Scholar
 13.M. Varchola, M. Drutarovsky, New high entropy element for FPGA based true random number generators, in Cryptographic Hardware and Embedded Systems (CHES), 2010 (Springer, 2010), pp. 351–365Google Scholar
Copyright information
Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.