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Circuits, Systems, and Signal Processing

, Volume 38, Issue 12, pp 5606–5622 | Cite as

Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic

  • Darjn EspositoEmail author
  • Davide De Caro
  • Gennaro Di Meo
  • Ettore Napoli
  • Antonio G. M. Strollo
Article
  • 185 Downloads

Abstract

Adaptive filters based on least-mean-square (LMS) algorithm are used in several applications in virtue of their good steady-state performance, numerical stability, and acceptable computational complexity. The hardware implementation of LMS filters requires a massive number of multipliers that significantly impact on the power consumption. Approximate computing, a design technique that trades off computation accuracy for better electrical performance, is a way to improve the energy efficiency of LMS filters. In this paper, we implement state-of-the-art approximate multipliers and evaluate their impact on the performance of the LMS algorithm. Moreover, a novel approximate multiplier, whose accuracy can be tuned at design time to better adapt to the application scenario, is proposed. Implementation results in 28-nm CMOS technology allow us to investigate the power versus quality trade-off of the considered LMS approximate filters in two different applications.

Keywords

LMS adaptive filters Approximate computing Approximate multipliers Power versus quality trade-off 

Notes

References

  1. 1.
    M. Alioto, Enabling the Internet of Things: From Integrated Circuits to Integrated Systems (Springer, Berlin, 2017)CrossRefGoogle Scholar
  2. 2.
    D.J. Allred, Y. Heejong, V. Krishnan, W. Huang, D.V. Anderson, LMS adaptive filters using distributed arithmetic for high throughput. IEEE Trans. Circuits Syst. I Regul. Pap. 52, 1327–1337 (2005).  https://doi.org/10.1109/TCSI.2005.851731 CrossRefGoogle Scholar
  3. 3.
    J.C.M. Bermudez, N.J. Bershad, A nonlinear analytical model for the quantized LMS algorithm-the arbitrary step size case. IEEE Trans. Signal Process. 44, 1175–1183 (1996).  https://doi.org/10.1109/78.502330 CrossRefGoogle Scholar
  4. 4.
    V.K. Chippa, S.Y. Chakradhar, K. Roy, A. Raghunathan, Analysis and characterization of inherent application resilience for approximate computing, in 50th ACM/EDAC/IEEE Design Automation Conference (DAC) (2013), pp. 1–9Google Scholar
  5. 5.
    K. Du, P. Varman, K. Mohanram, High performance reliable variable latency carry select addition, in Proceedings of Design, Automation and Test in Europe (DATE) (2012), pp. 1257–1262Google Scholar
  6. 6.
    D. Esposito, D. De Caro, A.G.M. Strollo, Variable latency speculative parallel prefix adders for unsigned and signed operands. IEEE Trans. Circuits Syst. I Regul. Pap. 63, 1200–1209 (2016).  https://doi.org/10.1109/TCSI.2016.2564699 MathSciNetCrossRefGoogle Scholar
  7. 7.
    D. Esposito, D. De Caro, E. Napoli, N. Petra, A.G.M. Strollo, On the use of approximate adders in carry-save multiplier-accumulators, in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) (2017), pp. 1–4Google Scholar
  8. 8.
    D. Esposito, A.G.M. Strollo, M. Alioto, Low-power approximate MAC unit, in Proceedings of IEEE PRIME 2017 Conference (2017), pp. 81–84Google Scholar
  9. 9.
    D. Esposito, G. Di Meo, D. De Caro, N. Petra, E. Napoli, A.G.M. Strollo, On the use of approximate multipliers in LMS adaptive filters, in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) (2018), pp. 1–5Google Scholar
  10. 10.
    B. Farhang-Boroujeny, Adaptive Filters: Theory and Applications (Wiley, Hobooken, 2013)CrossRefGoogle Scholar
  11. 11.
    V. Gupta, D. Mohapatra, S.P. Park, A. Raghunathan, K. Roy, IMPACT: IMPrecise adders for low-power approximate computing, in IEEE/ACM International Symposium on Low Power Electronics and Design (2011), pp. 409–414Google Scholar
  12. 12.
    J. Han, M. Orshansky, Approximate computing: an emerging paradigm for energy-efficient design, in 18th IEEE European Test Symposium (ETS) (2013), pp. 1–6Google Scholar
  13. 13.
    S. Haykin, Adaptive Filter Theory (Prentice-Hall, Englewood Cliffs, 2002)zbMATHGoogle Scholar
  14. 14.
    M. Horowitz, 1.1 Computing’s energy problem (and what we can do about it), in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (2014), pp. 10–14Google Scholar
  15. 15.
    M.T. Khan, S.R. Ahamed, VLSI realization of low complexity pipelined LMS filter using distributed arithmetic, in Proceedings TENCON 2017: 2017 IEEE Region 10 Conference (2017), pp. 433–438Google Scholar
  16. 16.
    M.T. Khan, S.R. Ahamed, F. Brewer, Low complexity and critical path based VLSI architecture for LMS adaptive filter using distributed arithmetic, in Proceedings of International Conference on VLSI Design and International Conference on Embedded Systems (VLSID) (2017), pp. 127–132Google Scholar
  17. 17.
    P. Kulkarni, P. Gupta, M. Ercegovac, Trading accuracy for power with an underdesigned multiplier architecture, in Proceedings of International Conference on VLSI Design (2011), pp. 346–351Google Scholar
  18. 18.
    Y. Lim, S. Parker, Discrete coefficient FIR digital filter design based upon an LMS criteria. IEEE Trans. Circuits Syst. 30(10), 723–739 (1983).  https://doi.org/10.1109/TCS.1983.1085295 CrossRefzbMATHGoogle Scholar
  19. 19.
    I.C. Lin, Y.M. Yang, C.C. Lin, High-performance low-power carry speculative addition with variable latency. IEEE Trans. Very Large Scale Int. Syst. 23, 1591–1603 (2015).  https://doi.org/10.1109/TVLSI.2014.2355217 CrossRefGoogle Scholar
  20. 20.
    M. Liu, M.-J. Wang, B.-Y. Song, An efficient architecture of the sign-error LMS adaptive filter, in 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) (2016), pp. 753–755Google Scholar
  21. 21.
    MATLAB, Acoustic Noise Cancellation (LMS) (2019). https://it.mathworks.com/help/dsp/examples/acoustic-noise-cancellation-lms.html. Accessed 6 April 2019
  22. 22.
    P.K. Meher, S.Y. Park, Critical-path analysis and low-complexity implementation of the LMS adaptive algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 61, 778–788 (2014).  https://doi.org/10.1109/TCSI.2013.2284173 CrossRefGoogle Scholar
  23. 23.
    I. Qiqieh, R. Shafik, G. Tarawneh, D. Sokolov, A. Yakovlev, Energy-efficient approximate multiplier using bit significance-driven logic compression, in Proceedings Design, Automation and Test in European Conference (DATE) (2017), pp. 7–12Google Scholar
  24. 24.
    S. Venkatachalam, S.-B. Ko, Design of power and area efficient approximate multipliers. IEEE Trans. Very Large Scale Integr. Syst. 25, 1782–1786 (2017)CrossRefGoogle Scholar
  25. 25.
    A.K. Verma, P. Brisk, P. Ienne, Variable latency speculative addition: a new paradigm for arithmetic circuit design, in Proceedings of Design, Automation and Test in Europe (DATE) (2008), pp. 1250–1255Google Scholar
  26. 26.
    B. Widrow, J.R. Glover, J.M. McCool, J. Kaunitz, C.S. Williams, R.H. Hearn, J.R. Zeidler, J. Eugene Dong, R.C. Goodlin, Adaptive noise cancelling: principles and applications. Proc. IEEE 63, 1692–1716 (1975).  https://doi.org/10.1109/PROC.1975.10036 CrossRefGoogle Scholar
  27. 27.
    N. Zhu, W.L. Goh, K.S. Yeo, An enhanced low-power high-speed Adder for Error-Tolerant application, in 12th International Symposium on Integrated Circuits (2009), pp. 69–72Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Electrical Engineering and Information TechnologyUniversity of Napoli FedericoNaplesItaly

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