Advertisement

Circuits, Systems, and Signal Processing

, Volume 38, Issue 4, pp 1506–1519 | Cite as

A CMOS Frequency Doubler from the Analog Cosine Mapping Function

  • Victor R. Gonzalez-DiazEmail author
  • Gregorio Zamora-Mejia
  • Jose F. Guerrero-Castellanos
  • Gerardo Mino-Aguilar
  • Richard Torrealba-Melendez
  • Franco Maloberti
Article
  • 200 Downloads

Abstract

This work presents the design of a new frequency doubler by a simple inductorless active network, without the exigency of additional quadrature signals. The frequency doubling function of the proposed circuit relies on the analog cosine mapping operation. The mapping circuit is possible in voltage mode as the circuit is based on two face-to-face CMOS inverters switched by the same differential input signal. The circuit is designed, with a simple set of functions, according to the nonlinear circuit’s nature. It was designed in a CMOS 0.18-\(\upmu \)m process with a doubling frequency up to \(8~\text{ GHz }\). The experimental results of the prototype on the mentioned frequency range show the frequency doubling operation with a phase noise figure of \(-\,130~\text{ dBc/Hz }\) @ \(10~\text{ KHz }\) offset from the carrier.

Keywords

Frequency conversion Analog circuits Phase-locked loops Circuit synthesis 

Notes

Acknowledgements

The authors thank M. C. Ignacio Juarez-Ramirez from INAOE Microelectronics Lab Mexico for the support with bonding wire of prototypes.

References

  1. 1.
    H. Adachi et al, Design of CMOS resonating push–push frequency doubler, in IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK), Kyoto (2014), p. 1–2Google Scholar
  2. 2.
    S. D’Amico, A. Donno, M. Conta, A. Baschirotto, A 6.1 mW 7.5–10.6 GHz PLL-based frequency synthesizer for IEEE 802.15.4a UWB transceivers. Analog Integr. Circuits Signal Process. 88(3), 383–389 (2016)CrossRefGoogle Scholar
  3. 3.
    G.S. Jeong, W. Kim, J. Park, T. Kim, H. Park, D.K. Jeong, A \(0.015-\text{ mm }^{2}\) Inductorless 32-GHz clock generator with wide frequency-tuning range in 28-nm CMOS technology. IEEE Trans. Circuits Syst. II: Express Briefs 64(6), 655–659 (2017)CrossRefGoogle Scholar
  4. 4.
    H. Jia, L. Kuang, Z. Wang, B. Chi, A W-band injection-locked frequency doubler based on top-injected coupled resonator. IEEE Trans. Microw. Theory Techn. 64(1), 210–218 (2016)CrossRefGoogle Scholar
  5. 5.
    I. Ju, C.D. Cheon, J.D. Cressler, A compact highly efficient high-power Ka-band SiGe HBT cascode frequency doubler with four-way input transformer Balun. IEEE Trans. Microw. Theory Techn. 66(6), 2879–2887 (2018)CrossRefGoogle Scholar
  6. 6.
    E. Monaco, M. Pozzoni, F. Svelto, A. Mazzanti, Injection-locked CMOS frequency doublers for \(\mu \)-wave and mm-wave applications. IEEE J. Solid-State Circuits 45(8), 1565–1574 (2010)CrossRefGoogle Scholar
  7. 7.
    J. Oh, J. Jang, C.Y. Kim, S. Hong, A W-band high-efficiency CMOS differential current-reused frequency doubler. IEEE Microw. Wirel. Comp. Lett. 25(5), 307–309 (2015)CrossRefGoogle Scholar
  8. 8.
    D.M. Pozar, Microwave Engineering, 4th edn. (Wiley, Hoboken, 2011)Google Scholar
  9. 9.
    J. Reyes-Rosales, V.R. Gonzalez-Diaz, J.F. Guerrero-Castellanos, New approximation for cosine wave mapping function to transistor level circuit, in Proceedings International Conference on Electronics, Communications and Computers (CONIELECOMP), Cholula Mex. (2015), p. 98–103Google Scholar
  10. 10.
    E. Seevinck, Simple, wide-range approximations to trigonometric and inverse trigonometric functions useful in real-time signal processing, in IEE Proceedings G—Electronic Circuits and Systems. Vol. 128, No. 1, p. 41–45 (1981)Google Scholar
  11. 11.
    A. Tsitouras, F. Plessas, Ultra-wideband, low-power, inductorless, 3.1-4.8 GHz, CMOS VCO. Circuits Syst. Signal Process. 30(2), 263–285 (2011)CrossRefzbMATHGoogle Scholar
  12. 12.
    L. Vera, J.R. Long, A DC-100 GHz active frequency doubler with a low-voltage multiplier core. IEEE J. Solid-State Circuits 50(9), 1963–1973 (2015)CrossRefGoogle Scholar
  13. 13.
    J.M.C. Wong, H.C. Luong, A 1.5-V 4-GHz dynamic-loading regenerative frequency doubler in a 0.35-\(\mu \)m CMOS process. IEEE Trans. Circuits Syst. II: Analog Digital Signal Process. 50(8), 450–455 (2003)CrossRefGoogle Scholar
  14. 14.
    J. Xu, J. Hu, B. Ciftcioglu, H. Wu, A 4–15-GHz ring oscillator based injection-locked frequency multiplier with built-in harmonic generation, in Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA (2013), p. 1–4Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Faculty of ElectronicsBUAPPueblaMexico
  2. 2.Department of Electrical, Computer, and Biomedical EngineeringUniversity of PaviaPaviaItaly

Personalised recommendations