Circuits, Systems, and Signal Processing

, Volume 38, Issue 4, pp 1793–1810 | Cite as

Reed–Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems

  • Gabriele Perrone
  • Javier VallsEmail author
  • Vicente Torres
  • Francisco García-Herrero


Several 100 Gbps Ethernet standards for backplane, copper cables and fiber optic that include forward error correction based on Reed–Solomon (RS) codes have been recently approved, being an important issue not only to achieve high data rates but also to keep a low latency. This paper presents two low-latency and high-throughput RS decoders suitable for those standards. We propose the use of a modified Enhanced Parallel iBM Algorithm as the key equation solver (KES) stage and a novel architecture for the error evaluation block, which is suited for this KES. Implementation results are given for the RS(528,514) and RS(544,514) codes over GF(\(2^{10}\)) that reach 100 Gbps when implemented in a 90 nm CMOS process.


Reed–Solomon Decoder architecture High throughput Low latency ePIBMA 


  1. 1.
    J. Baek, M.H. Sunwoo, Simplified degree computationless modified Euclid’s algorithm and its architecture, in 2007 IEEE International Symposium on Circuits and Systems (2007), pp. 905–908Google Scholar
  2. 2.
    R.D. Cideciyan, M. Gustlin, M.P. Li, J. Wang, Z. Wang, Next generation backplane and copper cable challenges. IEEE Commun. Mag. 51(12), 130–136 (2013)CrossRefGoogle Scholar
  3. 3.
    W. Ji, W. Zhang, X. Peng, Z. Liang, 16-channel two-parallel Reed–Solomon based forward error correction architecture for optical communications, in 2015 IEEE International Conference on Digital Signal Processing (DSP) (2015), pp. 239–243Google Scholar
  4. 4.
    H. Lee, A high-speed low-complexity Reed–Solomon decoder for optical communications. IEEE Trans. Circuits Syst. II Express Briefs 52(8), 461–465 (2005)CrossRefGoogle Scholar
  5. 5.
    H. Lee, High-speed VLSI architecture for parallel Reed–Solomon decoder. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11(2), 288–294 (2003)CrossRefGoogle Scholar
  6. 6.
    H. Lee, C.S. Choi, J. Shin, J.S. Ko, 100-Gb/s three-parallel Reed-Solomon based forward error correction architecture for optical communications, in SoC Design Conference, 2008. ISOCC ’08. International, vol. 01 (2008a), pp. I–265–I–268Google Scholar
  7. 7.
    J.D. Lee, M.H. Sunwoo, Three-parallel Reed–Solomon decoder using S-DCME for high-speed communications. J. Signal Process Syst. 66(1), 15–24 (2012). CrossRefGoogle Scholar
  8. 8.
    S. Lee, H. Lee, J. Shin, J.S. Ko, A high-speed pipelined degree-computationless modified Euclidean algorithm architecture for Reed–Solomon decoders, in: 2007 IEEE International Symposium on Circuits and Systems (2007), pp. 901–904Google Scholar
  9. 9.
    S. Lee, C.S. Choi, H. Lee, Two-parallel Reed–Solomon based FEC architecture for optical communications. IEICE Electron. Express 5(10), 374–380 (2008b)CrossRefGoogle Scholar
  10. 10.
    J.I. Park, H. Lee, Area-efficient truncated Berlekamp–Massey architecture for Reed–Solomon decoder. Electron. Lett. 47(4), 241–243 (2011)CrossRefGoogle Scholar
  11. 11.
    J.I. Park, J. Yeon, S.J. Yang, H. Lee, An ultra high-speed time-multiplexing Reed–Solomon-based FEC architecture, in SoC Design Conference (ISOCC), 2012 International (2012), pp. 451–454Google Scholar
  12. 12.
    D.V. Sarwate, N.R. Shanbhag, High-speed architectures for Reed–Solomon decoders. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 9(5), 641–655 (2001)CrossRefGoogle Scholar
  13. 13.
    H. Shao, L. Deutsch, J. Yuen, T. Truong, I. Reed, A VLSI design of a pipeline Reed–Solomon decoder. IEEE Trans. Comput. 34, 393–403 (1985). MathSciNetCrossRefzbMATHGoogle Scholar
  14. 14.
    L. Song, M.L. Yu, M.S. Shaffer, 10- and 40-Gb/s forward error correction devices for optical communications. IEEE J. Solid State Circuits 37(11), 1565–1573 (2002)CrossRefGoogle Scholar
  15. 15.
    Telecommunication Standardization Section, International Telecommunication Union (1996) ITU-T Recommendation G.975. Forward error correction for submarine systemsGoogle Scholar
  16. 16.
    Y. Wu, New scalable decoder architectures for Reed–Solomon codes. IEEE Trans. Commun. 63(8), 2741–2761 (2015)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.ABB SACEVittuoneItaly
  2. 2.Instituto de Telecomunicaciones y Aplicaciones Multimedia (ITEAM), Universitat Politècnica de ValènciaValènciaSpain
  3. 3.European University Miguel de CervantesValladolidSpain
  4. 4.ARIES Research CenterUniversidad Antonio de NebrijaMadridSpain

Personalised recommendations