Circuits, Systems, and Signal Processing

, Volume 38, Issue 4, pp 1482–1505 | Cite as

An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM

  • Bhupendra Singh ReniwalEmail author
  • Vikas Vijayvargiya
  • Pooran Singh
  • Nand Kishor Yadav
  • Santosh Kumar Vishvakarma
  • Devesh Dwivedi


In this paper, for the first time, a novel offset suppression technique is proposed to tackle the offset issue. The key idea is to improve bit error rate (BER) with an energy-efficient offset prediction-based sense amplifier (OPB-SA) for static random access memory (SRAM). The OPB-SA effectively compensates for the branch current mismatch due to threshold voltage (VTH) offset in SA sensing devices. Extensive simulation results, referring to an industrial hardware-calibrated UMC 65-nm CMOS technology, show that OPB-SA achieves 27.2, 20 and 11.1% offset reduction over current latch SA (CLSA), SA with inherent offset cancellation (SAOC) and offset-compensated current SA (OCCSA), respectively, without sacrificing performance. The OPB-SA features significant offset suppression capabilities with 31.3, 12.2 and 7% tighter offset distribution compared to CLSA, SAOC and OCCSA, respectively. The energy efficiency is 0.26fJ/bit, thus improving 61.04, 84.16 and 87.12% over SAOC, OCCSA and body bias SA (BBSA), respectively. The OPB-SA requires 0.72 ×, 0.8 × and 0.88 × less bit-line swings than CLSA, SAOC and OCCSA for targeted 0% BER. Hence, overall SRAM macro with proposed scheme exhibits a superior dynamic power metric over the conventional designs with 0.66 ×, 0.74 ×, 0.98 × and 0.81 × lower bit-line power consumption than CLSA, SAOC, OCCSA and BBSA, respectively.


SRAM Input-referred offset Power–delay product Differential current Process variation 


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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  • Bhupendra Singh Reniwal
    • 1
    Email author
  • Vikas Vijayvargiya
    • 2
  • Pooran Singh
    • 3
  • Nand Kishor Yadav
    • 4
  • Santosh Kumar Vishvakarma
    • 4
  • Devesh Dwivedi
    • 5
  1. 1.Department of Electrical & Electronics EngineeringBirla Institute of Technology & Science PilaniGoaIndia
  2. 2.Madanapalle Institute of Technology & ScienceAngalluIndia
  3. 3.Intel CorporationPenangMalaysia
  4. 4.Nanoscale Devices VLSI Circuits & System Design LabIndian Institute of Technology IndoreIndoreIndia
  5. 5.High Speeds Serial Link, Analog & Memory IP Development, Global FoundriesBangaloreIndia

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