FPGA Implementation of Lifting-Based Data Hiding Scheme for Efficient Quality Access Control of Images
In this paper, a hardware implementation of a data hiding technique is proposed for efficient quality access control of images using lifting-based discrete wavelet transformation (DWT). Host image is decomposed into n-level wavelet tiles. A binary watermark image is transmuted and embedded into high–high DWT coefficients using adaptive dither modulation technique without self-noise suppression. The embedding of external information into the host image will degrade the visual quality. This feature may be utilized for access control. At the decoder side, an authorized user can enjoy superior quality image by extracting watermark bits using minimum distance decoding. Field-programmable gate array-based hardware architecture is proposed for real-time implementation of the scheme. The experiment is done over a large number of benchmark images, and the results are found to be superior to the related work which is present in the literature. It is also seen that (a) in real-time processing, the scheme saves 89.53% power than the related implementation found in the literature, and (b) a very high throughput of 23.8 MB/s is achieved for watermarking encoder and decoder, respectively, at a maximum operating frequency of 130.14 MHz for the processing of (512 × 512) sized images.
KeywordsQuality access control Dither modulation Data hiding QIM FPGA
This study was supported by the Ministry of Science and Technology (MOST), Taiwan R.O.C., under Grant Number MOST 107-3113-E-155-001-CC2,106-3113-E-155-001-CC2, 106-2221-E-155-036, 105-3113-E-155-001, 104-3113-E-155-001, 103-3113-E-155-001, 103-2221-E-155-028-MY3.
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