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Circuits, Systems, and Signal Processing

, Volume 38, Issue 2, pp 774–790 | Cite as

Analysis of Systolic Penalties and Design of Efficient Digit-Level Systolic-like Multiplier for Binary Extension Fields

  • Bimal K. MeherEmail author
  • Pramod K. Meher
Article
  • 53 Downloads

Abstract

Systolic designs are considered as suitable candidate for high-speed VLSI realization for their inherent advantages of simplicity, regularity, modularity, and local interconnections. During the past few decades several systolic designs of finite field multipliers have been proposed in the literature. They are popularly used to achieve very high-throughput rate without any centralized control. But, all these designs incorporate heavy systolic penalties in terms of register complexity and latency of computation. We have analyzed here the hidden systolic penalties in those multipliers and proposed a digit-level systolic-like structure and a super-systolic-like structure for finite field multiplication. We have shown that the key issues to obtain such designs are the choice of design layout and digit size which substantially affect the register complexity, critical path, and latency. We have determined the optimal digit size and design layout to reduce the systolic penalties and at the same time to achieve lower critical path, higher-throughput rate, and lower latency with less register complexity with lower overall area complexity.

Keywords

Binary extension field Polynomial basis Trinomial Systolic Multiplier 

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of CSESilicon Institute of TechnologyBhubaneswarIndia
  2. 2.Research AdvisorC V Raman College of EngineeringBhubaneswarIndia

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