Circuits, Systems, and Signal Processing

, Volume 38, Issue 1, pp 173–190 | Cite as

Area-Efficient Dual-Mode Fused Floating-Point Three-Term Adder

  • K. ThiruvenkadamEmail author
  • J. Ramesh
  • Anjali S. Pillai


Floating-point addition is the most frequently used arithmetic operation in almost all general-purpose processors. This paper presents a dual-mode architecture for fused floating-point three-term adder. The traditional architecture for fused floating-point three-term adder is single-mode design where the addition of three operands takes place in a single unit. The existing improved architecture is also a single-mode design that incorporates few optimizations compared to the traditional fused floating-point three-term adder that would reduce area as well as delay. The proposed dual-mode architecture performs either a double-precision addition or two parallel single-precision additions in a single architecture based on the mode selection. The proposed architecture supports both normal and subnormal operations and also exceptional case handling like infinity, NaN and zero cases. The proposed architecture is implemented using both FPGA and ASIC, thus leading to efficient resource sharing, and the area gets reduced compared to two single-precision and a double-precision traditional and improved floating-point adder architectures.


Floating-point addition Single precision Double precision Dual mode FPGA ASIC 


  1. 1.
    A. Akkas, Dual-mode floating-point adder architectures. J. Syst. Archit. 54(12), 1129–1142 (2008)CrossRefGoogle Scholar
  2. 2.
    A. Akkas, Dual-mode quadruple precision floating-point adder, in Proceedings of the Euromicro Symposium Digital System (DSD’06) (2006), pp. 211–220Google Scholar
  3. 3.
    J.D. Bruguera, T. Lang, Floating-point fused multiply-add: reduced latency for floating-point addition, in 17th IEEE Symposium on Computer Arithmetic (2005), pp. 42–51Google Scholar
  4. 4.
    S. Galal, M. Horowitz, Energy-efficient floating-point unit design. IEEE Trans. Comput. 60(7), 913–922 (2011)MathSciNetCrossRefzbMATHGoogle Scholar
  5. 5.
    Y. Hida, X.S. Li, D.H. Bailey, Algorithms for quad-double precision floating point arithmetic, in Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 (2001), pp. 155–162Google Scholar
  6. 6.
    IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (IEEE, 1985)Google Scholar
  7. 7.
    IEEE standard 754-2008, IEEE Standard for Floating-Point Arithmetic. Technical Report (2008), pp. 1–70Google Scholar
  8. 8.
    M.K. Jaiswal, R.C.C. Cheung, M. Balakrishnan, Unified architecture for double/two-parallel single precision floating point adder. IEEE Trans. Circuits Syst. 61(7), 521–525 (2014)CrossRefGoogle Scholar
  9. 9.
    T. Lang, J.D. Bruguera, Floating-point multiply-add-fused with reduced latency. IEEE Trans. Comput. 53(8), 988–1003 (2004)CrossRefGoogle Scholar
  10. 10.
    G. Marcus, P. Hinojosa, A. Avila, J. Nolazco-FIores, A fully synthesizable single-precision, floating-point adder/substractor and multiplier in VHDL for general and educational use, in Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems (2004), pp. 319–323Google Scholar
  11. 11.
    V.G. Oklobdzija, An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis. IEEE Trans. Very Large Scale Integr. VLSI Syst. 2(1), 124–128 (1994)CrossRefGoogle Scholar
  12. 12.
    H. Saleh, E.E. Swartzlander, A floating-point fused add-subtract unit, in 51st Midwest Symposium on Circuits and Systems (2008), pp. 519–522Google Scholar
  13. 13.
    H.H. Saleh, E.E. Swartzlander, A floating-point fused dot product unit, in Proceedings of the IEEE International Conference Computer Design (2008), pp. 427–431Google Scholar
  14. 14.
    E.M. Schwarz, M. Schmookler, S.D. Trong, Hardware implementations of denormalized numbers, in Proceedings of the 16th IEEE Symposium on Computer Arithmetic Metic (2003), pp. 70–78Google Scholar
  15. 15.
    P.M. Seidel, G. Even, Delay-optimized implementation of IEEE floating-point addition. IEEE Trans. Comput. 53(2), 97–113 (2004)CrossRefGoogle Scholar
  16. 16.
    J. Sohn, E.E. Swartzlander, Improved architectures for a fused floating-point add-subtract unit. IEEE Trans. Circuits Syst. I Reg. Pap. 59(10), 2285–2291 (2012)MathSciNetCrossRefGoogle Scholar
  17. 17.
    J. Sohn, E.E. Swartzlander, A fused floating-point three-term adder. IEEE Trans. Circuits Syst. I Regul. Pap. 61(10), 2842–2850 (2014)MathSciNetCrossRefGoogle Scholar
  18. 18.
    E.E. Swartzlander, H.H. Saleh, Fused floating-point arithmetic for DSP, in Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers (2008), pp. 767–771Google Scholar
  19. 19.
    Y. Tao, G. Deyuan, F. Xiaoya, R. Xianglong, Three-operand floating-point adder, in IEEE 12th International Conference on Computer and Information Technology (2012), pp. 192–196Google Scholar
  20. 20.
    A.F. Tenca, Multi-operand floating-point addition, in Proceedings of the 19th IEEE Symposium on Computer Arithmetic (ARITH ‘09) (2009), pp. 161–168Google Scholar

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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringAnna University Regional CampusCoimbatoreIndia
  2. 2.Department of Electronics and Communication EngineeringPSG College of TechnologyCoimbatoreIndia

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