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Circuits, Systems, and Signal Processing

, Volume 38, Issue 1, pp 173–190 | Cite as

Area-Efficient Dual-Mode Fused Floating-Point Three-Term Adder

  • K. ThiruvenkadamEmail author
  • J. Ramesh
  • Anjali S. Pillai
Article
  • 44 Downloads

Abstract

Floating-point addition is the most frequently used arithmetic operation in almost all general-purpose processors. This paper presents a dual-mode architecture for fused floating-point three-term adder. The traditional architecture for fused floating-point three-term adder is single-mode design where the addition of three operands takes place in a single unit. The existing improved architecture is also a single-mode design that incorporates few optimizations compared to the traditional fused floating-point three-term adder that would reduce area as well as delay. The proposed dual-mode architecture performs either a double-precision addition or two parallel single-precision additions in a single architecture based on the mode selection. The proposed architecture supports both normal and subnormal operations and also exceptional case handling like infinity, NaN and zero cases. The proposed architecture is implemented using both FPGA and ASIC, thus leading to efficient resource sharing, and the area gets reduced compared to two single-precision and a double-precision traditional and improved floating-point adder architectures.

Keywords

Floating-point addition Single precision Double precision Dual mode FPGA ASIC 

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringAnna University Regional CampusCoimbatoreIndia
  2. 2.Department of Electronics and Communication EngineeringPSG College of TechnologyCoimbatoreIndia

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