Circuits, Systems, and Signal Processing

, Volume 37, Issue 4, pp 1479–1504 | Cite as

Design of 0.35-ps RMS Jitter 4.4–5.6-GHz Frequency Synthesizer with Adaptive Frequency Calibration Using 55-nm CMOS Technology

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Abstract

This paper demonstrates the design and implementation of a 5-GHz frequency synthesizer using 55-nm complementary metal-oxide semiconductor technology. The proposed synthesizer achieves an ultra-low 0.35-ps jitter with a high-resolution adaptive frequency calibration scheme that automatically chooses frequency-tuning curves and improves calibration accuracy. The proposed synthesizer employs a high-Q LC voltage-controlled oscillator, constant bandwidth, low, and even \(K_{\mathrm{VCO}}\) technique using thermometer-weighted capacitor calibration, a low-power divider, and a charge-pump (CP) circuit to achieve low jitter. The oscillator comprises a modified digitally controlled capacitor and varactor array, which extend the tuning range and minimize the phase noise. A matched differential CP is adopted to reduce reference spurs and phase-noise performance. The proposed frequency synthesizer achieves an output frequency of 4.4–5.6 GHz with a chip area of \(0.33\hbox { mm}^{2}\). The power consumption is 20 mW from a 1.2-V supply at 5 GHz, and the reference spur is −67.99 dBc. The measured root mean-square random jitter and phase noise are 0.35 ps and −110.04 dBc/Hz at 1 MHz, respectively.

Keywords

Frequency synthesizer Phase-locked loop Adaptive calibration Low jitter 
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Notes

Acknowledgements

This work was supported by the National Natural Science Foundation of China (No. 61474134).

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Copyright information

© Springer Science+Business Media, LLC 2017

Authors and Affiliations

  1. 1.Microelectronic Key Lab, Institute of Microelectronics, Chinese Academy of SciencesUniversity of Chinese Academy of SciencesBeijingChina

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