Circuits, Systems, and Signal Processing

, Volume 36, Issue 3, pp 1150–1168 | Cite as

A Flash ADC Tolerant to High Offset Voltage Comparators

  • António Couto-Pinto
  • Jorge R. Fernandes
  • Moisés Piedade
  • Manuel M. Silva


A conventional flash analog-to-digital converter (ADC) with a Wallace tree encoder ensures monotonicity and avoids missing codes, but still requires comparators with low offset voltage, which implies high area and power consumption. In this paper, we extend the purpose of this flash implementation, to allow the comparators to have extremely high offset voltages. This leads to a new approach toward the design of a flash ADC that does not require any type of calibration, allow easy porting among technologies and benefits from scaling. A statistical study is presented to demonstrate the effectiveness of the new method, and a modification is proposed to ensure full-range operation. It is shown that a proposed N-bit ADC has a performance equivalent to an \((N-m)\)-bit conventional flash ADC, with considerable gains in area and power consumption, with less design effort. The design flow of the OST ADC, with the necessary steps, is presented. A circuit, employing minimum dimension transistors, was fabricated in 0.13-\({\upmu }\hbox {m}\) CMOS and used as a proof of concept for the ADCs proposed here.


Analog–digital conversion Flash ADC Wallace tree Stochastic errors Offset voltage 



This work has been supported by FCT, Fundação para a Ciência e a Tecnologia (Portugal), under projects PEst-OE/EEI/LA0021/2013 and DISRUPTIVE (EXCL/EEI-ELC/0261/2012).


  1. 1.
    S. Akiyama, T. Waho, A 6-bit low-power compact flash ADC using current-mode threshold logic gates, in 2006 IEEE International Symposium on Circuits and Systems, 21–24 May 2006, p. 4. doi:  10.1109/iscas.2006.1693490
  2. 2.
    M. Ceekala, K. El-Sankary, E. El-Masry, Stochastic ADC with random U-quadratic distributed reference voltages to uniformly distribute comparators trip point. Analog Integr. Circuits Signal Process. 74(2), 461–465 (2013). doi: 10.1007/s10470-012-9996-3 CrossRefGoogle Scholar
  3. 3.
    H.Y. Chang, C.Y. Yang, A high-speed low-power calibrated flash ADC, in 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1–5 June 2014, pp. 2369–2372. doi:  10.1109/iscas.2014.6865648
  4. 4.
    D.C. Daly, A.P. Chandrakasan, A 6-bit, 0.2 V to 0.9 V highly digital flash ADC with comparator redundancy. IEEE J. Solid-State Circuits 44(11), 3030–3038 (2009). doi: 10.1109/jssc.2009.2032699 CrossRefGoogle Scholar
  5. 5.
    P.G. Drennan, C.C. McAndrew, Understanding MOSFET mismatch for analog design. IEEE J. Solid-State Circuits 38(3), 450–456 (2003). doi: 10.1109/jssc.2002.808305 CrossRefGoogle Scholar
  6. 6.
    P.M. Figueiredo, J.C. Vital, Low kickback noise techniques for CMOS latched comparators, in Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS ’04, vol 531, 23–26 May 2004, pp. I-537–I-540. doi:  10.1109/iscas.2004.1328250
  7. 7.
    M.P. Flynn, C. Donovan, L. Sattler, Digital calibration incorporating redundancy of flash ADCs. IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process. 50(5), 205–213 (2003). doi: 10.1109/tcsii.2003.811435 CrossRefGoogle Scholar
  8. 8.
    M. Goswami, D.M. Varma, Saloni, B.R. Singh, Reduced comparator high speed low power ADC using 90 nm CMOS technology. Analog Integr. Circuits Signal Process. 74(1), 267–278 (2013). doi: 10.1007/s10470-012-9959-8 CrossRefGoogle Scholar
  9. 9.
    B.V. Hieu, S. Choi, J. Seon, Y. Oh, C. Park, J. Park, H. Kim, T. Jeong, A new approach to thermometer-to-binary encoder of flash ADCs-bubble error detection circuit, in 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 7–10 August 2011, pp. 1–4. doi:  10.1109/mwscas.2011.6026403
  10. 10.
    G. Keskin, J. Proesel, J.O. Plouchart, L. Pileggi, Exploiting combinatorial redundancy for offset calibration in flash ADCs. IEEE J. Solid-State Circuits 46(8), 1904–1918 (2011). doi: 10.1109/jssc.2011.2157255 CrossRefGoogle Scholar
  11. 11.
    Y.Z. Lin, C.W. Lin, S.J. Chang, A 5-bit 3.2-GS/s flash ADC with a digital offset calibration scheme. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18(3), 509–513 (2010). doi: 10.1109/tvlsi.2009.2013628 CrossRefGoogle Scholar
  12. 12.
    B. Murmann, ADC Performance Survey 1997–2015 [Online].
  13. 13.
    M.J.M. Pelgrom, A.C.J. Duinmaijer, A.P.G. Welbers, Matching properties of MOS transistors. IEEE J. Solid-State Circuits 24(5), 1433–1439 (1989). doi: 10.1109/jssc.1989.572629 CrossRefGoogle Scholar
  14. 14.
    P. Pereira, J.R. Fernandes, M.M. Silva, Wallace tree encoding in folding and interpolation ADCs, in IEEE International Symposium on Circuits and Systems, 2002. ISCAS 2002, vol 501 (2002), pp. I-509–I-512. doi:  10.1109/iscas.2002.1009889
  15. 15.
    E. Sall, M. Vesterbacka, Thermometer-to-binary decoders for flash analog-to-digital converters, in 18th European Conference on Circuit Theory and Design, 2007. ECCTD 2007, 27–30 August 2007, pp. 240–243. doi:  10.1109/ecctd.2007.4529581
  16. 16.
    Y.S. Shu, A 6b 3GS/s 11 mW fully dynamic flash ADC in 40 nm CMOS with reduced number of comparators, in 2012 Symposium on VLSI Circuits (VLSIC), 13–15 June 2012, pp. 26–27. doi:  10.1109/vlsic.2012.6243772
  17. 17.
    L. Sumanen, M. Waltari, K. Halonen, A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters, in The 7th IEEE International Conference on Electronics, Circuits and Systems, 2000. ICECS 2000, vol 31 (2000), pp. 32–35. doi:  10.1109/icecs.2000.911478
  18. 18.
    C.S. Wallace, A suggestion for a fast multiplier. IEEE Trans. Electr. Comput. EC–13(1), 14–17 (1964). doi: 10.1109/pgec.1964.263830 CrossRefzbMATHGoogle Scholar
  19. 19.
    A. Waters, S. Leuenberger, F. Farahbakhshian, U.K. Moon, Analysis and performance trade-offs of linearity calibration for stochastic ADCs, in 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2014, 7–10 December 2014, pp. 207–210. doi:  10.1109/icecs.2014.7049958
  20. 20.
    S. Weaver, B. Hershberg, P. Kurahashi, D. Knierim, U.K. Moon, Stochastic flash analog-to-digital conversion. IEEE Trans. Circuits Syst. I Regul. Pap. 57(11), 2825–2833 (2010). doi: 10.1109/tcsi.2010.2050225 MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  1. 1.INESC-ID-Lisboa, Department of Electronics, Telecommunications and Computers EngineeringInstituto Superior de Engenharia de LisboaLisbonPortugal
  2. 2.INESC-ID-Lisboa, Instituto Superior TécnicoUniversidade de LisboaLisbonPortugal

Personalised recommendations