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Circuits, Systems, and Signal Processing

, Volume 35, Issue 5, pp 1481–1505 | Cite as

Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

  • Masoumeh Souri
  • Mohammad Bagher Ghaznavi-GhoushchiEmail author
Article

Abstract

Digitally controlled oscillators are the main cores in all-digital phase-locked loops (ADPLL), which are important for determining the range of frequency and power consumption in ADPLLs. In the conventional digitally controlled oscillator (DCO) designs, one single band of operation is assigned to the DCO. The following paper presents a new approach in the design of DCOs, which works in dual-band and wide-band modes with a control unit. In dual-band mode, the DCO works in two different ranges of frequencies simultaneously via digital control bits. The wide-band DCO (WBDCO) works in one wider range of frequencies consecutively. It seems that in the wide-band DCO, the gap width for the dual-band DCO (DBDCO) is zero. The previously mentioned designs allow the designer to have standard frequencies with the help of direct or multiplied frequencies. So, we can have a trade-off between power and performance. This means that we can have low power consumption in low-frequency applications and vice versa. The proposed designs are based on using digitally controlled capacitors, current starving gates and Schmitt triggers in critical points of the DCO loop, while preserving coarse and fine tunings. The non-delay linearity factors are clearly investigated and resolved with the use of a new combined control unit. The simulations of the proposed designs are performed in Hspice with a voltage of \(\mathrm{VDD}=1.8\) v in 180 nm CMOS technology for 64- and 128-bit input coarse codes. Our simulation and evaluation results showed that in the dual-band DCO, a 14.8 ps jitter was calculated at 134 MHz with 1.2131 mW power consumption, while in the wide band with overlap mode, a 68.7 ps jitter was measured at 184.61 MHz with 1.604 mW power consumption. Our designs are proper for reconfigurable and multi-standard ADPLL designs.

Keywords

Digitally controlled oscillator (DCO) Low-power DCO  Jitter  Dual-band DCO Wide-band DCO Digitally controlled capacitors (DCV) All-digital phase-locked loop (ADPLL) Phase frequency detector (PFD) 

Notes

Acknowledgments

The authors wish to thank the following persons for their helps: Dr. Mohsen Jalali of Shahed university, Saied Souri of Qazvin University, Mahmoud Pourbafrani of Esfahan university, Mahshid Rahimi of Shahab Danesh University, Arash Abadian of Tehran University, Naser Erfani-Majd of Amirkabir University of Technology, Saberi Moqadam, Somayye Badvi, Masuomeh Rahimi and Somayye Yousefi. The authors wish to thank anonymous reviewers for their fruitful comments and questions during the review phase. The first author specially wishes to thank her beloved parents for their support and encouragements during the development of this work.

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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Masoumeh Souri
    • 1
  • Mohammad Bagher Ghaznavi-Ghoushchi
    • 1
    Email author
  1. 1.Department of Electrical EngineeringShahed UniversityTehranIran

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