Circuits, Systems, and Signal Processing

, Volume 35, Issue 2, pp 367–383 | Cite as

Phase Interpolator with Improved Linearity

  • George SouliotisEmail author
  • Costas Laoudias
  • Fotis Plessas
  • Nikolaos Terzopoulos


An analog phase interpolator with improved step linearity is presented in this paper. The linearity is improved by setting the time constant of the output nodes in suitable value and by employing a fine trimming technique. The performance and the improved linearity have been verified with post-layout simulations using a well-established CMOS 65 nm technology and transistors with standard threshold voltages. The clock frequency is at 2.5 GHz and the core voltage supply at 1.2 V. Its low phase noise makes the circuit suitable for high-speed systems where low jitter performance is required.


Phase interpolator Clock and data recovery SerDes 


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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • George Souliotis
    • 1
    Email author
  • Costas Laoudias
    • 1
  • Fotis Plessas
    • 2
  • Nikolaos Terzopoulos
    • 3
  1. 1.Department of PhysicsUniversity of PatrasPatrasGreece
  2. 2.Department of Electrical and Computer EngineeringUniversity of ThessalyVolosGreece
  3. 3.Department of Computing and Communication Technologies, Faculty of Technology, Design and EnvironmentOxford Brookes UniversityWheatley, OxfordUK

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