Built-in Self Test Power and Test Time Analysis in On-chip Networks

Mahdieh Nadi Senejani; Mahdiar Ghadiry; Chia Yee Ooi; Muhammad Nadzir Marsono

doi:10.1007/s00034-014-9892-4

Circuits, Systems, and Signal Processing

April 2015, Volume 34, Issue 4, pp 1057–1075 | Cite as

Built-in Self Test Power and Test Time Analysis in On-chip Networks

Authors
Authors and affiliations

Mahdieh Nadi Senejani
Mahdiar GhadiryEmail author
Chia Yee Ooi
Muhammad Nadzir Marsono

Article

First Online: 23 September 2014

Received: 08 May 2013

Revised: 08 September 2014

Accepted: 08 September 2014

245 Downloads
2 Citations

Abstract

Testing power dissipation of on-chip networks (NoC) is an interesting topic, which is still unexplored specially analytically. In this paper, a transistor level model is proposed to study the testing power and area of testing logic in a mesh NoC using IEEE 1149.1-based approach. For the purpose of verification, HSPICE simulation and FPGA implementation are used. The switching activities are computed using a special purpose cycle-accurate NoC simulator. At the end, the model is used to calculate test power and spot the most energy consuming and area occupying component of a typical NoC testing circuit.

Keywords

On-chip networks Test JTAG Energy Analytical model Built-in self test

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Appendix

Multiplexer Energy ($E_\mathrm{MUX}$)

Capacitances of a common N to 1 multiplexer can be modelled as follows. According to the sample transmission-gate-based 4 to 1 multiplexer shown in Fig. 11, the total capacitance is divided into four categories being total gate ($C_\mathrm{gt}$), junction ($C_\mathrm{jn}$), inverters on complement select inputs ($C_\mathrm{inv}$), and interconnection wire capacitances($C_\mathrm{w}$). Therefore, the energy model for a generalised $N$ to 1 multiplexer could be expressed as

$$\begin{aligned} E_\mathrm{MUX}(N)=\frac{1}{2} V_\mathrm{dd}^2 (\alpha _\mathrm{gt} C_\mathrm{gt}+ \alpha _{j} C_{j}+ \alpha _\mathrm{inv} C_\mathrm{inv}+ \alpha _w C_{w})+E_{st_\mathrm{MUX}} \end{aligned}$$

(24)

The total gate capacitance times related switching activity is given as

$$\begin{aligned} \alpha _\mathrm{gt} C_\mathrm{gt}=\sum \limits _{i=1}^{\log _2^N}2^i\times \left( C_\mathrm{g_{n}} +C_\mathrm{g_{p}}{}\right) \alpha _{s_i} \end{aligned}$$

(25)

The total junction capacitance times related switching activity is given as

$$\begin{aligned} \alpha _{j} C_\mathrm{jn}=2\sum \limits _{i=1}^{\log _2^n}2^i\times \left( C_{\mathrm{j_{n}}_i} + C_{\mathrm{j_{p}}_i} \right) \alpha _{{j}_i}, \end{aligned}$$

(26)

where $C_\mathrm{j_{n}}$ and $C_\mathrm{j_{p}}$ are junction capacitances of NMOS and PMOS, respectively. The total inverters’ capacitance times related switching activities is given as

$$\begin{aligned} \alpha _\mathrm{inv} C_\mathrm{inv}=\sum \limits _{i=1}^{\log _2^n}2^i\times (C_\mathrm{g_{n}}+C_\mathrm{g_{p}}+ C_\mathrm{j_{n}}+C_\mathrm{j_{p}})\alpha _{s_i} \end{aligned}$$

(27)

Fig. 11
Common 4 to 1 multiplexer implemented by transmission gate. Complement of select signals ($s_0, s_1, ..., s_n$) connected to nmos FETs are not shown in this figure

D-Latch and D Flip-Flop Energies ($E_{D-Latch}$ and $E_{DFF}$)

Similarly, the total energy of a D-latch module as illustrated in Fig. 12 can be modelled as

$$\begin{aligned} E_\mathrm{{D-latch}}&=\frac{1}{2}V_\mathrm{dd}^2\alpha C_\mathrm{{D-latch}}+E_{\mathrm{st}_\mathrm{{D-latch}}}\end{aligned}$$

(28)

$$\begin{aligned} \alpha C_\mathrm{{D-latch}}&=\alpha _\mathrm{clk} \left( {C_\mathrm{g_{n}}}_1+ {C_\mathrm{g_{p}}}_1+{C_\mathrm{g_{n}}}_2+ {C_\mathrm{g_{p}}}_2\right) +\alpha _{d} \left( {C_\mathrm{j_{n}}}_1+{C_\mathrm{j_{p}}}_1+{C_\mathrm{j_{n}}}_2+{C_\mathrm{j_{p}}}_2\right) \nonumber \\&\quad + \alpha _{d} \left( C_{\mathrm{inv}_1}+ C_{\mathrm{inv}_2}+ C_{\mathrm{inv}_3}\right) , \end{aligned}$$

(29)

where $\alpha _\mathrm{clk}$ and $\alpha _{d}$ are the clock and D input switching activities, and $inv3$ is the inverter to provide $clkb$ signal. The $C_\mathrm{inv}$ is defined as

$$\begin{aligned} C_\mathrm{inv}=\left( {C_\mathrm{g_{n}}}+{C_\mathrm{g_{p}}}+{C_\mathrm{j_{n}}}+{C_\mathrm{j_{p}}} \right) \end{aligned}$$

(30)

Fig. 12
Common schematic of D-latch implemented by transmission gate

In addition, according to Fig. 13, the energy of a master-slave DFF is expressed as

$$\begin{aligned} E_\mathrm{DFF}=2E_{\mathrm{D-latch}}+E_\mathrm{inv} \end{aligned}$$

(31)

NAND Energy

A common CMOS energy is implemented according to Fig. 14 and its energy consumption is given as

$$\begin{aligned} E_\mathrm{NAND}=\frac{1}{2}V_\mathrm{dd}^2\alpha C_\mathrm{NAND}+E_{\mathrm{st}_\mathrm{NAND}}, \end{aligned}$$

(32)

where $\alpha C_\mathrm{NAND}$ is expressed as

$$\begin{aligned} \alpha C_\mathrm{NAND}&= \alpha _A \left( {C_\mathrm{g_{n}}}+{C_\mathrm{g_{p}}}\right) +\alpha _B \left( {C_\mathrm{g_{n}}}+{C_\mathrm{g_{p}}}\right) \nonumber \\&+\,\alpha _\mathrm{out}\left( 2{C_\mathrm{j_{p}}}+ {C_\mathrm{j_{n}}}\right) \end{aligned}$$

(33)

Fig. 14
Schematic of a common CMOS NAND gate

XOR Energy

A common CMOS energy is implemented according to Fig. 15 and its energy consumption is given as

$$\begin{aligned} E_\mathrm{XOR}=\frac{1}{2}V_\mathrm{dd}^2\alpha C_\mathrm{XOR}+E_{\mathrm{st}_\mathrm{XOR}}, \end{aligned}$$

(34)

where $\alpha C_\mathrm{XOR}$ is given as

$$\begin{aligned} \alpha C_\mathrm{XOR}=&\alpha _A C_\mathrm{invA} + \alpha _B C_\mathrm{invB}\nonumber \\&+\quad \alpha _A(C_\mathrm{g_{p1}}+C_\mathrm{g_{n2}}+C_\mathrm{g_{p2}}+C_\mathrm{g_{n1}}) \end{aligned}$$

(35)

Fig. 15
Schematic of a common XOR gate implemented by transmission gate

OR Energy

A common CMOS energy is implemented according to Fig. 16 and its energy consumption is given as

$$\begin{aligned} E_\mathrm{OR}=\frac{1}{2}V_\mathrm{dd}^2\alpha C_\mathrm{OR}+E_{\mathrm{st}_\mathrm{OR}}, \end{aligned}$$

(36)

where $\alpha C_\mathrm{OR}$ is given as

$$\begin{aligned} \alpha C_\mathrm{OR}=&\alpha _A \left( {C_\mathrm{g_{n}}}+{C_\mathrm{g_{p}}}\right) +\alpha _B \left( {C_\mathrm{g_{n}}}+{C_\mathrm{g_{n}}} \right) \nonumber \\&\quad +\quad \alpha _\mathrm{out}\left( C_\mathrm{j_{p}}+ 2{C_\mathrm{j_{n}}}+C_\mathrm{inv}\right) \end{aligned}$$

(37)

Fig. 16
Schematic of a common OR gate implemented by conventional CMOS style

Wire Energy

$$\begin{aligned} E_{W}(\alpha ,L,W,C)=\frac{1}{2} \alpha V_\mathrm{dd}^2 W L C \end{aligned}$$

(38)

where, $\alpha $, $W$, $L$, and $C$ are the switching activity, width, length, and the sheet capacitance of the wire respectively.

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Authors and Affiliations

Mahdieh Nadi Senejani
- 1
Mahdiar Ghadiry
- 2
Email author
Chia Yee Ooi
- 1
Muhammad Nadzir Marsono
- 1

1.Faculty of Electrical EngineeringUniversiti Teknologi MalaysiaJohor BahruMalaysia
2.Department of Computer EngineeringIslamic Azad UniversityArak BranchIran

Built-in Self Test Power and Test Time Analysis in On-chip Networks

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