Advertisement

Circuits, Systems, and Signal Processing

, Volume 31, Issue 3, pp 987–1015 | Cite as

FPGA-Implementation of Discrete Wavelet Transform with Application to Signal Denoising

  • Mohammed BahouraEmail author
  • Hassan Ezzaidi
Article

Abstract

This paper presents new architectures for real-time implementation of the forward/inverse discrete wavelet transforms and their application to signal denoising. The proposed real-time wavelet transform algorithms present the advantage to ensure perfect reconstruction by equalizing the filter path delays. The real-time signal denoising algorithm is based on the equalized filter paths wavelet shrinkage, where the noise level is estimated using only few samples. Different architectures of these algorithms are implemented on FPGA using Xilinx System Generator for DSP and XUP Virtex-II Pro development board. These architectures are evaluated and compared in terms of reconstruction error, denoising performance and resource utilization.

Keywords

Wavelet transform Signal denoising Soft-thresholding Filter group delay Pipelining FPGA 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    K. Andra, C. Chakrabarti, T. Acharya, A VLSI architecture for lifting-based forward and inverse wavelet transform. IEEE Trans. Signal Process. 50(4), 966–977 (2002) CrossRefGoogle Scholar
  2. 2.
    K. Azadet, C.J. Nicole, Low-power equalizer architectures for high-speed modems. IEEE Commun. Mag. 36(10), 118–126 (1998) CrossRefGoogle Scholar
  3. 3.
    M. Bahoura, H. Ezzaidi, Real-time implementation of discrete wavelet transform on FPGA, in IEEE 10th International Conference on Signal Processing (ICSP), Oct. (2010), pp. 191–194 CrossRefGoogle Scholar
  4. 4.
    M. Bahoura, H. Ezzaidi, FPGA—implementation of parallel and sequential architectures for adaptive noise cancelation. Circ. Syst. Signal Process. 1–28. doi: 10.1007/s00034-011-9310-0
  5. 5.
    M. Bahoura, J. Rouat, Wavelet speech enhancement using the teager energy operator. IEEE Signal Process. Lett. 8, 10–12 (2001) CrossRefGoogle Scholar
  6. 6.
    M. Bahoura, J. Rouat, Wavelet speech enhancement based on time-scale adaptation. Speech Commun. 48(12), 1620–1637 (2006) CrossRefGoogle Scholar
  7. 7.
    S.G. Chang, B. Yu, M. Vetterli, Adaptive wavelet thresholding for image denoising and compression. IEEE Trans. Image Process. 9(9), 1532–1546 (2000) MathSciNetzbMATHCrossRefGoogle Scholar
  8. 8.
    J. Chilo, T. Lindblad, Hardware implementation of 1D wavelet transform on an FPGA for infrasound signal classification. IEEE Trans. Nucl. Sci. 55(1), 9–13 (2008) CrossRefGoogle Scholar
  9. 9.
    D.L. Donoho, Nonlinear wavelet methods for recovering signals, images, and densities from indirect and noisy data. Proc. Symp. Appl. Math. 47, 173–205 (1993) MathSciNetGoogle Scholar
  10. 10.
    D.L. Donoho, De-noising by soft-thresholding. IEEE Trans. Inf. Theory 41, 613–627 (1995) MathSciNetzbMATHCrossRefGoogle Scholar
  11. 11.
    A. Grzeszczak, M.K. Mandal, S. Panchanathan, VLSI implementation of discrete wavelet transform. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 4(4), 421–433 (1996) CrossRefGoogle Scholar
  12. 12.
    K.A. Kotteri, S. Barua, A.E. Bell, J.E. Carletta, A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting. IEEE Trans. Circuits Syst. II, Express Briefs 52(5), 256–260 (2005) CrossRefGoogle Scholar
  13. 13.
    S. Mallat, A theory for multiresolution signal decomposition: the wavelet representation. IEEE Trans. Pattern Anal. Mach. Intell. 11, 674–693 (1989) zbMATHCrossRefGoogle Scholar
  14. 14.
    J. Martinez, R. Cumplido, C. Feregrino, An FPGA-based parallel sorting architecture for the Burrows Wheeler transform, in Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, (2005) 7 pp. Google Scholar
  15. 15.
    Matlab, Signal Processing Blockset 7 User’s Guide (The MathWorks, Inc., Natick, 2010) Google Scholar
  16. 16.
    K.G. Oweiss, A. Mason, Y. Suhail, A.M. Kamboh, K.E. Thomson, A scalable wavelet transform VLSI architecture for real-time signal processing in high-density intra-cortical implants. IEEE Trans. Circuits Syst. 54(6), 1266–1278 (2007) CrossRefGoogle Scholar
  17. 17.
    K.K. Parhi, T. Nishitani, VLSI architectures for discrete wavelet transforms. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 1(2), 191–202 (1993) CrossRefGoogle Scholar
  18. 18.
    S. Poornachandra, Wavelet-based denoising using subband dependent threshold for ECG signals. Digit. Signal Process. 18(1), 49–55 (2008) CrossRefGoogle Scholar
  19. 19.
    R. Quian Quiroga, Obtaining single stimulus evoked potentials with wavelet denoising. Physica D: Nonlinear Phenom. 145(3–4), 278–292 (2000) zbMATHCrossRefGoogle Scholar
  20. 20.
    L. Su, G. Zhao, De-Noising of ECG signal using translation-invariant wavelet De-Noising method with improved thresholding, in 27th Annual International Conference of the IEEE EMBS, Sept. (2005), pp. 5946–5949 Google Scholar
  21. 21.
    P.E. Tikkanen, Nonlinear wavelet and wavelet packet denoising of electrocardiogram signal. Biol. Cybern. 80(4), 259–267 (1999) zbMATHCrossRefGoogle Scholar
  22. 22.
    A. Vera, U. Meyer-Baese, M. Pattichis, An FPGA based rapid prototyping platform for wavelet coprocessors, in Proceedings of SPIE—The International Society for Optical Engineering, vol. 6576, pp. 657615.1–657615.10 (2007) Google Scholar
  23. 23.
    C. Wang, W.S. Gan, Efficient VLSI architecture for lifting-based discrete wavelet packet transform. IEEE Trans. Circuits Syst. II 54(5), 422–426 (2007) CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Department of EngineeringUniversité du Québec à RimouskiRimouskiCanada
  2. 2.Department of Applied SciencesUniversité du Québec à ChicoutimiChicoutimiCanada

Personalised recommendations