FPGA-Implementation of Discrete Wavelet Transform with Application to Signal Denoising
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This paper presents new architectures for real-time implementation of the forward/inverse discrete wavelet transforms and their application to signal denoising. The proposed real-time wavelet transform algorithms present the advantage to ensure perfect reconstruction by equalizing the filter path delays. The real-time signal denoising algorithm is based on the equalized filter paths wavelet shrinkage, where the noise level is estimated using only few samples. Different architectures of these algorithms are implemented on FPGA using Xilinx System Generator for DSP and XUP Virtex-II Pro development board. These architectures are evaluated and compared in terms of reconstruction error, denoising performance and resource utilization.
KeywordsWavelet transform Signal denoising Soft-thresholding Filter group delay Pipelining FPGA
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- 4.M. Bahoura, H. Ezzaidi, FPGA—implementation of parallel and sequential architectures for adaptive noise cancelation. Circ. Syst. Signal Process. 1–28. doi: 10.1007/s00034-011-9310-0
- 14.J. Martinez, R. Cumplido, C. Feregrino, An FPGA-based parallel sorting architecture for the Burrows Wheeler transform, in Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, (2005) 7 pp. Google Scholar
- 15.Matlab, Signal Processing Blockset 7 User’s Guide (The MathWorks, Inc., Natick, 2010) Google Scholar
- 20.L. Su, G. Zhao, De-Noising of ECG signal using translation-invariant wavelet De-Noising method with improved thresholding, in 27th Annual International Conference of the IEEE EMBS, Sept. (2005), pp. 5946–5949 Google Scholar
- 22.A. Vera, U. Meyer-Baese, M. Pattichis, An FPGA based rapid prototyping platform for wavelet coprocessors, in Proceedings of SPIE—The International Society for Optical Engineering, vol. 6576, pp. 657615.1–657615.10 (2007) Google Scholar