Journal of Computer Science and Technology

, Volume 17, Issue 6, pp 718–730 | Cite as

Lower bound estimation of hardware resources for scheduling in high-level synthesis

  • Shen Zhaoxuan 
  • Jong Ching Chuen 
Regular Papers

Abstract

In high-level synthesis of VLSI circuits, good lower bound prediction can efficiently narrow down the large space of possible designs. Previous approaches predict the lower bound by relaxing or even ignoring the precedence constraints of the data flow graph (DFG), and result in inaccuracy of the lower bound. The loop folding and conditional branch were also not considered. In this paper, a new stepwise refinement algorithm is proposed, which takes consideration of precedence constraints of the DFG to estimate the lower bound of hardware resources under time constraints. Processing techniques to handle multi-cycle, chaining, pipelining, as well as loop folding and mutual exclusion among conditional branches are also incorporated in the algorithm. Experimental results show that the algorithm can produce a very tight and close to optimal lower bound in reasonable computation time.

Keywords

lower bound estimation chaining pipelining mutual exclusion high-level synthesis 

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References

  1. [1]
    Hu Y, Carlson B S. A unified algorithm for the estimation and scheduling of data flow graphs.Journal of Circuit Systems and Computers, June, 1996, 6(3): 287–318.CrossRefGoogle Scholar
  2. [2]
    Tiruvuri G, Chung M. Estimation of lower bounds in scheduling algorithms for high-level synthesis.ACM Trans. Design Automation of Electronic Systems, Apr., 1998, 3(2): 162–180.CrossRefGoogle Scholar
  3. [3]
    Narasimhan M, Ramannjam J. On lower bounds for scheduling problems in high-level synthesis. InProc. 2000 Design Automation Conference, Los Angeles, CA, USA, June, 2000, pp.546–551.Google Scholar
  4. [4]
    Jain R, Parker A C, Park N. Predicting system-level area and delay for pipelined and non-pipelined designsIEEE Trans. CAD-ICAS, 1992, 11(8): 955–965.Google Scholar
  5. [5]
    Timmer A H, Heijligers M J M, Jess J A G. Fast system-level area-delay curve prediction. InProc. 1st Asian Pacific Conference on Hardware Description Languages Standards and Applications, Brisbane, Australia, Dec., 1993, pp.198–207.Google Scholar
  6. [6]
    Nourani M, Papachristou C. A layout estimation algorithm for RTL datapaths. InProc. 30th Design Automation Conferences, Dallas, TX, USA, 1993, pp.285–291.Google Scholar
  7. [7]
    Timmer A H, Jess J A G. Execution interval analysis under resource constraints. InProc. International Conference on Computer Aided Design, Santa Clara, CA, USA, Nov., 1993, pp.454–459.Google Scholar
  8. [8]
    Sharma A, Jain R. Estimating architectural resources and performance for high-level synthesis applications. InProc. 30th Design Automation Conferences, Dallas, TX, USA, 1993, pp.355–360.Google Scholar
  9. [9]
    Wehn N, Glesner M, Vielhauer C. Estimating lower bounds in high-level synthesis. InIFIP Trans. VLSI 93: Proc. IFIP TC10/WG10.5 Int. Conf. VLSI, Grenoble, France, Sept., 1993, pp.261–270.Google Scholar
  10. [10]
    Ohm S Y, Kurdahi F J, Dutt N. Comprehensive lower bound estimation from behavioral descriptions. InProc. International Conference on Computer Aided Design, San Jose, CA, USA, Nov., 1994, pp.182–187.Google Scholar
  11. [11]
    Phm S Y, Kurdahi F J, Dutt N D. A unified lower bound estimation technique for high-level synthesis.IEEE Trans. CAD-ICAS, May, 1997, 16(5): 458–472.Google Scholar
  12. [12]
    Hu Y, Ghouse A, Carlson B S. Lower bounds on the iteration time and the number of resources for functional pipelined data flow graphs. InProc. International Conference on Computer Design, Cambridge, MA, USA, Oct., 1993, pp.21–24.Google Scholar
  13. [13]
    Hwang C T, Lee J H, Hsu Y C. A formal approach to the scheduling problem in high level synthesis.IEEE Trans. CAD-ICAS, 1991, 10(4): 464–475.Google Scholar
  14. [14]
    Gebotys C H, Elmasry M I. Global optimization approach for architectural synthesis.IEEE Trans. CAD-ICAS, Sept., 1993, 12(9): 1266–1278.Google Scholar
  15. [15]
    Hwang C T, Hsu Y C. Zone scheduling.IEEE Trans. CAD-ICAS, Jul., 1993, 12(7): 926–934.Google Scholar
  16. [16]
    Wilson T C, Grewal G W, Banerji D K. An ILP solution for simultaneous scheduling, allocation, and binding in multiple block synthesis. InProc. International Conference on Computer Design, Cambridge, MA, USA, 1994, pp.581–586.Google Scholar
  17. [17]
    Rim M, Jain R. Estimating lower-bound performance of schedules using a relaxation technique. InProc. International Conference on Computer Design, Cambridge, MA, USA, 1992, pp. 290–294.Google Scholar
  18. [18]
    Rim M, Jain R. Lower-bound performance estimation for the high-level synthesis scheduling problem.IEEE Trans. CAD-ICAS, Apr., 1994, 13(4): 451–458.Google Scholar
  19. [19]
    Chaudhuri S, Walker R A. Computing lower bounds on functional units before scheduling. InProc. 7th International Symposium on High-Level Synthesis, Ontario, Canada, May, 1994, pp.36–41.Google Scholar
  20. [20]
    Langevin M, Cerny E. A recursive technique for computing lower-bound performance of schedules. InProc. International Conference on Computer Design, Cambridge, MA, USA, 1993, pp.16–20.Google Scholar
  21. [21]
    Shen Z X, Jong C C. Functional area lower bound and upper bound on multicomponent selection for interval scheduling.IEEE Trans. CAD-ICAS, July, 2000, 19(7): 745–759.Google Scholar
  22. [22]
    Jha P K, Dutt N D. Rapid estimation for parameterized components in high-level synthesis.IEEE Trans. VLSI systems, Sept., 1993, 1(3): 296–303.CrossRefGoogle Scholar
  23. [23]
    Mintz D, Dangelo C. Timing estimation for behavioral descriptions. InProc. 7th International Symposium on High-Level Synthesis, Ontario, Canada, May, 1994, pp.42–47.Google Scholar
  24. [24]
    Rabaey J M, Potkonjak M. Estimating implementation bounds for real time DSP application specific circuits.IEEE Trans. CAD-ICAS, June, 1994, 13(6): 669–683.Google Scholar
  25. [25]
    Kruse L, Schmidt E, Jochens G, Stammermann A, Nebel W. Lower bound estimation for low power high-level synthesis In.Proc. 13th Int. Symposium on System Synthesis, Madrid, Spain, 2000, pp.180–185.Google Scholar
  26. [26]
    Paulin P G, Knight J P. Force-directed scheduling for the behavioral synthesis of ASIC’s.IEEE Trans. CAS-ICAS. June, 1989, 8(6): 661–679.Google Scholar
  27. [27]
    Lee T F, Wu A C H, Lin Y L, Gajski D D. A transformation-based method for loop folding.IEEE Trans. CAD-ICAS, Apr., 1994, 13(4): 439–450.Google Scholar
  28. [28]
    Lee T F, Wu A C H, Gajski D D, Lin Y L. An effective methodology for functional pipelining. InProc. International Conference on Computer Aided Design, Santa Clara, CA, USA, 1992, pp.230–233.Google Scholar
  29. [29]
    Hwang C T, Hsu Y C, Lin Y L. PLS: A scheduler for pipeline synthesis.IEEE Trans. CAD-ICAS, Sept. 1993, 12(9): 1279–1286.Google Scholar
  30. [30]
    Passos N L, Sha E H M, Bass S C. Loop pipelining for scheduling multi-dimensional systems via rotation. InProc. 31st Design Automation Conference, San Diego, CA, USA, 1994, pp.485–490.Google Scholar
  31. [31]
    Wakabayashi K, Tanaka H. Global scheduling independent of control dependencies based on condition vectors. InProc. 29th Design Automation Conference, Anaheim, CA, USA, 1992, pp.112–115.Google Scholar
  32. [32]
    Springer D L, Thomas D E. Exploiting the special structure of conflict and compatibility graphs in high-level synthesis.IEEE Trans. CAD-ICAS, July, 1994, 13(7): 843–856.Google Scholar
  33. [33]
    Timmer A H, Heijligers J M, Stok, L, Jess J A G. Module selection and scheduling using unrestricted libraries. InProc. of the European Conference on Design Automation with the European Event in ASIC Design, Paris, France, Feb., 1993, pp.547–551.Google Scholar
  34. [34]
    Park N, Parker A C. Sehwa, a software package for synthesis of pipelines from behavioral specification.IEEE Trans. CAD-ICAS, Mar., 1988, 7(3): 356–370.Google Scholar
  35. [35]
    Parker A C, Pizarro J T, Milnar M. MAHA: A program for datapath synthesis. InProc. 23rd Design Automation Conference, Las Vegas, NV, USA, 1986, pp.461–466.Google Scholar
  36. [36]
    Kim T K, Yonezawa N, Liu W S J, Liu C L. A scheduling algorithm for conditional resource sharing — A hierarchical reduction approach.IEEE Trans. CAD-ICAS, Apr., 1994, 13(4): 425–438.Google Scholar

Copyright information

© Science Press, Beijing China and Allerton Press Inc. 2002

Authors and Affiliations

  • Shen Zhaoxuan 
    • 1
  • Jong Ching Chuen 
    • 1
  1. 1.School of Electrical and Electronic EngineeringNanyang Technological UniversitySingapore

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