Algorithm and implementation of parallel multiplication in a mixed number system
- 20 Downloads
This paper presents a high-speed multiplication algorithm for the mixed number system of the ordinary binary number and the symmetric redundant binary number. It is implemented with the multivalued logic theory, and 3-valued and 2-valued circuits are used. The 3-valued circuit proposed in this paper is an emitter-coupled logic circuit with high speed, simplicity and powerful functions. A 3-valued ECL threshold gate can simultaneously produce six types of one-variable operations. The array multiplier, designed with the algorithm and the circuits, is fast and simple, and is suitable for building LSI. It can be used in a high-speed computer just as an ordinary binary multiplier.
- A. Avizienis, A Study of Redundant Number Representions for Parallel Digital Computers, Ph.D. Thesis University of Illinois. Urbama, Illinoin, 5 (1960).Google Scholar
- C.Y. Chow and J.E. Robwrison, Logical Design of a Redundant Binary Adder, Proc. 4th Symp. Computer Arithmetic, 10 (1978), 109–115.Google Scholar