Algorithm and implementation of parallel multiplication in a mixed number system

  • Luo Yinfang 
Regular Papers

DOI: 10.1007/BF02943345

Cite this article as:
Luo, Y. J. of Comput. Sci. & Technol. (1988) 3: 203. doi:10.1007/BF02943345


This paper presents a high-speed multiplication algorithm for the mixed number system of the ordinary binary number and the symmetric redundant binary number. It is implemented with the multivalued logic theory, and 3-valued and 2-valued circuits are used. The 3-valued circuit proposed in this paper is an emitter-coupled logic circuit with high speed, simplicity and powerful functions. A 3-valued ECL threshold gate can simultaneously produce six types of one-variable operations. The array multiplier, designed with the algorithm and the circuits, is fast and simple, and is suitable for building LSI. It can be used in a high-speed computer just as an ordinary binary multiplier.

Copyright information

© Science Press, Beijing China and Allerton Press Inc. 1988

Authors and Affiliations

  • Luo Yinfang 
    • 1
  1. 1.Institute of Computing TechnologyAcademia SinicaBeijingChina

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