Simultaneous multithreading fault tolerance processor
Trusted Computing Architecture
Received:
Abstract
Transient fault detection mechanism is added to simultaneous multithreading architecture. By exploiting both ILP (Instruction Level Parallelism) and TLP (Thread Level Parallelism), Simultaneous Multithreading (SMT) Fault Tolerance Processor can be expected to achieve better tradeoff between performance and hardware cost than traditional Fault Tolerance Processors. Detailed simulations of 3 of SPEC95 benchmarks show that executing two redundant programs on the fault-tolerant microarchitecture takes only 40%–61% longer than running a single version of the program. The new instruction fetch algorithm enhances the performance by 0.4% ∼1% to most of the benchmarks we choose randomly.
Key words
simultaneous multithreading rault tolerance TLP (Thread Level Parallelism) fetch policyCLC number
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References
- [1]Theo U. A Survey of Processors with Explicit Multithreading.ACM Computing Surveys, 2003,35(1):29–63.CrossRefGoogle Scholar
- [2]Smith J E, Sohi G S. The Microarchitecture of Superscalar Processors,Proceedings of the IEEE. New York: IEEE Press, Dec 1995. 1609–1624.Google Scholar
- [3]Tullsen D M, Eggers S J, Emer J,et al. Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading.ACM Transactions on Computer Systems, 1997,15(3):322–354.CrossRefGoogle Scholar
- [4]Reinhardt S K, Mukherjee S S. Transient Fault Detection via Simultaneous Multithreading.Proceedings of the 27th Annual International Symposium on Computer Architecture, New York: ACM Press, 2000. 25–36.Google Scholar
- [5]Mukherjee S S, Kontz M, Reinhardt S K. Detailed Design and Evaluation of Redundant Multithreading Alternatives.Proceedings of the 29th Annual International Symposium on Computer Architecture. New York: ACM Press, 2002. 99–110.CrossRefGoogle Scholar
- [6]Rotenberg E. AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessor.Proceedings of FTCS'99, New York. IEEE Press, 1999, 84–91.Google Scholar
- [7]Johnson B W, Fault-Tolerant Microprocessor-Based Systems.IEEE Micro, 1984,4(6):6–21.CrossRefGoogle Scholar
- [8]Tullsen D M, Eggers S J, Emer J S,et al. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor.Proceedings of the 23rd Annual International Symposium on Computer Architecture. New York: ACM Press, 1996. 191–202.Google Scholar
- [9]Tullsen D M, Eggers S J, Levy H M. Simultaneous Multithreading: Maximizing on-Chip Parallelism.Proceedings of the 22th Annual International Symposium on Computer Architecture. New York: ACM Press, 1995, 392–340.Google Scholar
- [10]Burger D, Austin T M. The SimpleScalar Tool Set. Version2. 0,ACM SIGARCH Computer Architecture, 1997,25 (3):13–25.CrossRefGoogle Scholar
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