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Pipeline interleaving design for FIR, IIR, and FFT array processors

  • Liang-Gee Chen
  • Yeu-Shen Jehng
  • Tzi-Dar Chiueh
Article

Abstract

In this paper, a floating point multiply- and-accumulate (FMAC) processor capable of running the FIR, IIR, and FFT algorithms is proposed. This processor executes many independent FMAC operations circularly without causing any hazard. The algorithmic processing is decomposed into independent subprocesses, each of which executes a FMAC group and all of the subprocesses are activated in turn. The projection method of VLSI array processors is used to map the data flow of FIR, IIR, and FFT into subprocesses so that the algorithms can be successfully executed by the processor in the way of pipeline interleaving. Because of the 100% utilization of pipeline, a very good performance is achieved.

Keywords

Fast Fourier Transform Digital Signal Processing Finite Impulse Response Dependence Graph Digital Signal Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Kluwer Academic Publishers 1995

Authors and Affiliations

  • Liang-Gee Chen
    • 1
  • Yeu-Shen Jehng
    • 1
  • Tzi-Dar Chiueh
    • 1
  1. 1.Department of Electrical EngineeringNational Taiwan UniversityTaipeiTaiwan 10764, R.O.C.

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